From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF4431F872D; Sun, 8 Feb 2026 09:05:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770541512; cv=none; b=luLf8NIA5No6Kf/6ne1wMxJc7W7sbdHiTij7kAC/5GPiSRTpl8yHqlV1cXbHD0kwGrbNqAAC+G15MnI0VzTB14ACNAfbI3a2XsDL0HSFhUsNo6V/TMQEDDN8sYcJebqyrnBiocuq2LXMgam1+MWNlaqqP42bZUJlTkwGmI/9hOM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770541512; c=relaxed/simple; bh=IjmY924MOYXvkiLpvJeWlpv0ss7WAiLTx8eQzbe2plA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=nW6CfILtXPIVi2UusNJpL8BpHd3NY+FZ4iZTcTgxBN51wZ2aVJrovSCMfS77pbskX5DNVQSNbHaHIR01jums9aMZYg0Cs3m2tI3/8hN+jmKHODi0A04ZLAP0VjQ8C5MUlCDTH+xmoTI5MMBTrRWrrPwctwBCty8KoQu8rIQsusY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZMX/O+/J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZMX/O+/J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55920C4CEF7; Sun, 8 Feb 2026 09:05:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770541512; bh=IjmY924MOYXvkiLpvJeWlpv0ss7WAiLTx8eQzbe2plA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ZMX/O+/JZLFWflZrouC0QHZQL6g9FCEY1RMUJOdg2nQEGmCsuU8YKaT2byMVyx88P 8ef4kZ19ifyfzCGUqMezJJOu81y9mU7gtnoyTz4eh9PE6xVVdm3zPdkobvr9VHT5CO EQfb2vrgDCDKiEhJikflBusA7ADOdlC8noWOz4swVYcH9SbhPV+/9VxlMKoOI20dr6 ax3fjANsRsM7w/RQFm9T+XmVmMneMkNT8b6pqDR0vO/Rg/ctdZBUO4vfupeDa3W3/P qQn5NOBOOY6W1UfeMpLMB34ELgGOv4kDYuajVF+Li+F9hJt3QAVtK5Pn7kpuVnRfaO 0JPKZy4VF1jmA== Message-ID: Date: Sun, 8 Feb 2026 10:05:08 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8550: add cpu interconnect nodes To: webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> <20260207-sm8550-ddr-bw-scaling-v1-2-d96c3f39ac4b@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/02/2026 02:28, Aaron Kling via B4 Relay wrote: > From: Aaron Kling > > Add the interconnect entry for each cpu, with 3 different paths: > - CPU to Last Level Cache Controller (LLCC) > - Last Level Cache Controller (LLCC) to DDR > - L3 Cache from CPU to DDR interface > > Signed-off-by: Aaron Kling > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 49 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > This patch should be squashed. You add interconnect and use it, otherwise it is pretty pointless or even negatively impacting (syncing without interconnect paths). Best regards, Krzysztof