From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B249D1F3B8C; Tue, 4 Mar 2025 10:13:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083213; cv=none; b=Pb6ZcKeEz+joQCzf7ciLkqkaKkqUtUkJ2ak4DpzNjHoofqGFGz5DdINKMxsAK1kQsyVuiby2G43Gkt8dWPIwfv4XUevoEHf7LSYtdm1d+Ae4lKKAHUs2vo8R+nBZTA/5nD7PspVYWb17It2eT0lysJSY1Q5htEJEs1dp+vSyqTg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083213; c=relaxed/simple; bh=tSly4mCMCg7dVdmVWaL/taV9g1SQHNObtoFQnE+k5hY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=nZlV7x3FljeV1Vx9tMYFeHppIt/MW79/GkY1IAii5bD4YH90vyQDLkNLDQI5ZLA57qQd1WeJN2Snmt+l4VsRVoCPLWoc039e55qhcKxiiymhpHMSz2UH6hUdEKpmY563rtGCDaPXD/yoo7lYmfXa5Y5SyC0NwmJf9+L3zt94F0U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WlQOsWhN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WlQOsWhN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33F49C4CEE5; Tue, 4 Mar 2025 10:13:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741083213; bh=tSly4mCMCg7dVdmVWaL/taV9g1SQHNObtoFQnE+k5hY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=WlQOsWhNXid8j95Bwvji3nwiUxShDmNuzqHiVbnq7s00AOocTk1+QxICKYRb2U+Cx j7BRgA2bZOFVWj7swi+Dp0sD2HCeLJ9g8V420t7xw3X9F1uam/GaQ3YnLikaagvvkh Q+RMA+1ovszha6KLoiij5AeSuyk8Bu5CJfIWK2DXk5a0owQPw7WVvCJpVXvc/JaIJy Tuog+FDKfFw0YK/65KHO/IWpph9TMKlt8EIHgNgPSvBv+qidT0etNvRHvO/kMaol73 blhkmzBX27bfkDpaGkWFCPFBnwRCZP3h5091iLVGlT9QfIOjCB3+E1WBaxla8T9sZX OEWxTqOJev85g== Message-ID: Date: Tue, 4 Mar 2025 11:13:29 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores To: Hugues KAMBA MPIANA , sudeep.holla@arm.com Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org References: <20250303170012.469576-1-hugues.kambampiana@arm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/03/2025 18:00, Hugues KAMBA MPIANA wrote: > Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to > enable support for secondary CPU cores. > > This update facilitates symmetric multiprocessing (SMP) support on > the Corstone1000 Fixed Virtual Platform (FVP), allowing the > secondary cores to be properly initialised and utilised. > > Only FVP platform will have SMP support and hence the secondary cpu definitions > are not added to corstone1000.dtsi. > > Signed-off-by: Hugues KAMBA MPIANA > --- > arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++ > arch/arm64/boot/dts/arm/corstone1000.dtsi | 2 +- > 2 files changed, 25 insertions(+), 1 deletion(-) > No, nothing improved. Provide detailed changelog after the ---. Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. Best regards, Krzysztof