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Wed, 8 Oct 2025 04:26:55 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AIHrVq-NOQMk Date: Wed, 08 Oct 2025 10:26:35 +0200 From: "Arnd Bergmann" To: "Manivannan Sadhasivam" , "Lorenzo Pieralisi" Cc: "Vincent Guittot" , "Chester Lin" , "Matthias Brugger" , "Ghennadi Procopciuc" , "NXP S32 Linux Team" , bhelgaas@google.com, jingoohan1@gmail.com, =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , "Rob Herring" , krzk+dt@kernel.org, "Conor Dooley" , Ionut.Vicovan@nxp.com, "Larisa Grigore" , "Ghennadi Procopciuc" , ciprianmarian.costea@nxp.com, "Bogdan Hamciuc" , "Frank Li" , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, "Niklas Cassel" Message-Id: In-Reply-To: <4rghtk5qv4u7vx4nogctquu3skvxis4npxfukgtqeilbofyclr@nhkrkojv3syh> References: <20250919155821.95334-1-vincent.guittot@linaro.org> <20250919155821.95334-2-vincent.guittot@linaro.org> <4rghtk5qv4u7vx4nogctquu3skvxis4npxfukgtqeilbofyclr@nhkrkojv3syh> Subject: Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, Oct 8, 2025, at 00:28, Manivannan Sadhasivam wrote: > On Tue, Oct 07, 2025 at 05:41:55PM +0200, Lorenzo Pieralisi wrote: >> On Mon, Sep 22, 2025 at 11:51:07AM +0530, Manivannan Sadhasivam wrote: >> >> [...] >> >> > > + /* >> > > + * non-prefetchable memory, with best case size and >> > > + * alignment >> > > + */ >> > > + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>; >> > >> > s/0x82000000/0x02000000 >> > >> > And the PCI address really starts from 0x00000000? I don't think so. >> >> Isn't the DWC ATU programmed to make sure that the PCI memory window DT >> provides _is_ the PCI "bus" memory base address ? >> >> It is a question, I don't know the DWC inner details fully. >> >> I don't get what you mean by "I don't think so". Either the host controller >> AXI<->PCI translation is programmable, then the PCI base address is what >> we decide it is or it isn't. >> > > As per the binding, I/O PCI address already starts from 0x0. How can you have > two OB mappings with same PCI address? I/O space and memory space can use the same bus addresses, since they are disambiguated by the type in the actual PCIe transactions. We usually assume that I/O space port numbers start at 0 (as done here), while PCI memory ranges are identity-mapped to the CPU physical address they are mapped at, but in this case the physical address window is outside of the low 4GB range, so an identity map at 0x58.0x00000000 woulds prevent the use of 32-bit BARs, and mapping something in the low bus address range is the only possibility. On the other hand, what looks like a bug to me is that the CPU physical address range for the PCI BAR space overlaps with the the physical addresses for RAM at 0x80000000 and on-chip devices at 0x40000000. This probably works fine as long as the total PCI memory space assignment stays below 0x40000000 but would fail once addresses actually start clashing. Maybe the memory space can be split into two windows like <0x82000000 0x0 0x00000000 0x58 0x00000000 0x0 0x40000000>, // 1GB 32-bit non-pref <0xc2000000 0x1 0x00000000 0x59 0x00000000 0x6 0x00000000>; // 24GB 64-bit pref The 64-bit window could be either prefetchable or non-prefetchable in this case. If there is only one programmable window for memory space, that would probably have to be limited to 1GB non-prefetchable for the normal 32-bit BARs. Arnd