From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A17CC77B7E for ; Tue, 2 May 2023 15:21:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234565AbjEBPVU (ORCPT ); Tue, 2 May 2023 11:21:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234407AbjEBPVH (ORCPT ); Tue, 2 May 2023 11:21:07 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A9F519D for ; Tue, 2 May 2023 08:21:03 -0700 (PDT) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 342DAHRq004639; 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Tue, 2 May 2023 17:20:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2F2CF2278B4; Tue, 2 May 2023 17:20:47 +0200 (CEST) Received: from [10.201.21.93] (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 2 May 2023 17:20:46 +0200 Message-ID: Date: Tue, 2 May 2023 17:20:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v8 01/10] ARM: dts: stm32: Add alternate pinmux for ethernet Content-Language: en-US To: Steffen Trumtrar , CC: Krzysztof Kozlowski , Maxime Coquelin , , References: <20230411083045.2850138-1-s.trumtrar@pengutronix.de> <20230411083045.2850138-2-s.trumtrar@pengutronix.de> From: Alexandre TORGUE In-Reply-To: <20230411083045.2850138-2-s.trumtrar@pengutronix.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_09,2023-04-27_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Steffen On 4/11/23 10:30, Steffen Trumtrar wrote: > Add another option for the ethernet0 pins. > It is almost identical to ethernet0_rgmii_pins_c apart from TXD0/1. > > This is used on the Phycore STM32MP1. > > Signed-off-by: Steffen Trumtrar > --- > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index a9d2bec990141..1c97db4dbfc6d 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -341,6 +341,56 @@ pins1 { > }; > }; > > + ethernet0_rgmii_pins_d: rgmii-3 { > + pins1 { > + pinmux = , /* ETH_RGMII_CLK125 */ > + , /* ETH_RGMII_TXD0 */ > + , /* ETH_RGMII_TXD1 */ > + , /* ETH_RGMII_TXD2 */ > + , /* ETH_RGMII_TXD3 */ > + , /* ETH_RGMII_TX_CTL */ > + ; /* ETH_MDC */ > + bias-disable; > + drive-push-pull; > + slew-rate = <2>; > + }; > + pins2 { > + pinmux = ; /* ETH_MDIO */ > + bias-disable; > + drive-push-pull; > + slew-rate = <0>; > + }; > + pins3 { > + pinmux = , /* ETH_RGMII_RXD0 */ > + , /* ETH_RGMII_RXD1 */ > + , /* ETH_RGMII_RXD2 */ > + , /* ETH_RGMII_RXD3 */ > + , /* ETH_RGMII_RX_CLK */ > + ; /* ETH_RGMII_RX_CTL */ > + bias-disable; > + }; > + }; > + > + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-8 { Mistake here, it should be rgmii-sleep-3 > + pins1 { > + pinmux = , /* ETH_RGMII_CLK125 */ > + , /* ETH_RGMII_GTX_CLK */ > + , /* ETH_RGMII_TXD0 */ > + , /* ETH_RGMII_TXD1 */ > + , /* ETH_RGMII_TXD2 */ > + , /* ETH_RGMII_TXD3 */ > + , /* ETH_RGMII_TX_CTL */ > + , /* ETH_MDIO */ > + , /* ETH_MDC */ > + , /* ETH_RGMII_RXD0 */ > + , /* ETH_RGMII_RXD1 */ > + , /* ETH_RGMII_RXD2 */ > + , /* ETH_RGMII_RXD3 */ > + , /* ETH_RGMII_RX_CLK */ > + ; /* ETH_RGMII_RX_CTL */ > + }; > + }; > + > ethernet0_rmii_pins_a: rmii-0 { > pins1 { > pinmux = , /* ETH1_RMII_TXD0 */