From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: forbidden405@outlook.com,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v2 5/5] dt-bindings: clock: hisilicon,clock-reset-controller: add Hi3798MV200 SoC support
Date: Tue, 20 Feb 2024 11:15:37 +0100 [thread overview]
Message-ID: <ec0f1536-098c-42da-993a-a98f68f4eff1@linaro.org> (raw)
In-Reply-To: <20240217-clk-mv200-v2-5-b782e4eb66f7@outlook.com>
On 17/02/2024 13:52, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@outlook.com>
>
> This SoC is similar to Hi3798CV200.
>
> Also document the specific DLL regs and add an example for it.
>
> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
> ---
> .../clock/hisilicon,clock-reset-generator.yaml | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
> index d37cd892473e..8ee844574eda 100644
> --- a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
> +++ b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
> @@ -44,12 +44,17 @@ properties:
> - hisilicon,hi3519-crg
> - hisilicon,hi3798cv200-crg
> - hisilicon,hi3798cv200-sysctrl
> + - hisilicon,hi3798mv200-crg
> + - hisilicon,hi3798mv200-sysctrl
> - const: syscon
> - const: simple-mfd
>
> reg:
> maxItems: 1
>
> + ranges:
> + maxItems: 1
> +
> '#clock-cells':
> const: 1
>
> @@ -87,6 +92,12 @@ properties:
> description: |
> Reset controller for Hi3798CV200 GMAC module
>
> +patternProperties:
> + '.*-dll@[0-9a-f]+':
> + type: object
> + description: |
> + eMMC/SD delay-locked-loop (DLL) register subnode
NAK, now all of the syscons have the DLL node?
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-02-20 10:15 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-17 12:52 [PATCH RFC v2 0/5] clk: hisilicon: add support for Hi3798MV200 Yang Xiwen via B4 Relay
2024-02-17 12:52 ` [PATCH RFC v2 1/5] dt-bindings: clock: histb-clock: Add missing common clock and Hi3798MV200 specific clock definition Yang Xiwen via B4 Relay
2024-02-20 10:10 ` Krzysztof Kozlowski
2024-02-20 10:12 ` Yang Xiwen
2024-02-20 10:16 ` Krzysztof Kozlowski
2024-02-20 14:06 ` Yang Xiwen
2024-02-20 16:13 ` Krzysztof Kozlowski
2024-02-20 16:19 ` Yang Xiwen
2024-02-20 16:25 ` Krzysztof Kozlowski
2024-02-20 16:31 ` Yang Xiwen
2024-02-20 17:06 ` Krzysztof Kozlowski
2024-02-20 17:29 ` Yang Xiwen
2024-02-21 7:27 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 2/5] clk: hisilicon: add CRG driver for Hi3798MV200 SoC Yang Xiwen via B4 Relay
2024-02-20 10:11 ` Krzysztof Kozlowski
2024-02-20 10:14 ` Yang Xiwen
2024-02-20 10:17 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 3/5] dt-bindings: clock: merge all hisilicon clock bindings to hisilicon,clock-reset-generator Yang Xiwen via B4 Relay
2024-02-20 10:14 ` Krzysztof Kozlowski
2024-02-20 10:52 ` Yang Xiwen
2024-02-20 10:59 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 4/5] dt-bindings: mfd: syscon: Add hisilicon,sdmmc-sap-dll compatible Yang Xiwen via B4 Relay
2024-02-17 12:52 ` [PATCH RFC v2 5/5] dt-bindings: clock: hisilicon,clock-reset-controller: add Hi3798MV200 SoC support Yang Xiwen via B4 Relay
2024-02-20 10:15 ` Krzysztof Kozlowski [this message]
2024-02-20 10:16 ` Yang Xiwen
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