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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id z5-20020ac24f85000000b004b5480edf67sm4176567lfs.36.2023.01.01.07.49.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Jan 2023 07:49:05 -0800 (PST) Message-ID: Date: Sun, 1 Jan 2023 16:49:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v8 02/10] arm64: dts: qcom: Add base SM8550 dtsi Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan References: <20221230202230.2493494-1-abel.vesa@linaro.org> <20221230202230.2493494-3-abel.vesa@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20221230202230.2493494-3-abel.vesa@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 30/12/2022 21:22, Abel Vesa wrote: > Add base dtsi for SM8550 SoC and includes base description of > CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved > memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, > interconnect, thermal sensor, cpu cooling maps and SMMU nodes > which helps boot to shell with console on boards with this SoC. > > Co-developed-by: Neil Armstrong > Signed-off-by: Neil Armstrong > Signed-off-by: Abel Vesa > Reviewed-by: Konrad Dybcio > Reviewed-by: Sai Prakash Ranjan > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 3519 ++++++++++++++++++++++++++ > 1 file changed, 3519 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > new file mode 100644 > index 000000000000..a9514fcd6109 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -0,0 +1,3519 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0 0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + #cooling-cells = <2>; > + L2_0: l2-cache { > + compatible = "cache"; You miss cache-level properties in all cache nodes. > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { Messed indentation, > + compatible = "cache"; > + }; > + }; > + }; > + Best regards, Krzysztof