Re: [PATCH net-next 10/12] net: stmmac: tc956x: add TC956x/QPS615 support

Xilin Wu
2026-05-06T14:35:49Z

On 5/6/2026 10:19 PM, Andrew Lunn wrote:
> On Wed, May 06, 2026 at 08:59:01PM +0800, Xilin Wu wrote:
>> On 5/1/2026 11:54 PM, Alex Elder wrote:
>>> + /* AXI Configuration */
>>> + axi = &td->axi;
>>> + axi->axi_lpi_en = 1;
>>> + axi->axi_wr_osr_lmt = 31;
>>> + axi->axi_rd_osr_lmt = 31;
>>> + /* All sizes (2^2..2^8) are supported */
>>> + axi->axi_blen_regval = DMA_AXI_BLEN_MASK;
>>> + plat->axi = axi;
>>> +
>>> + plat->mac_port_sel_speed = speed;
>>> + plat->flags = STMMAC_FLAG_MULTI_MSI_EN | STMMAC_FLAG_TSO_EN;
>>
>> I got WoL working only after adding STMMAC_FLAG_USE_PHY_WOL here. I guess
>> it's required, since the driver clocks down the MAC/PMA/XPCS in its suspend
>> hook?
>
> Nice to see somebody testing WoL.
>
> In your testing, is it the PHY doing the WoL, or the MAC? I assume
> PHY.
>
> If i remember the DT correctly, the PHY interrupt is connected to a
> SoC GPIO, not a GPIO of this chip. So for your board, it is the SoCs
> GPIO controllers ability to perform the wake which is
> important. However, where the PHY interrupt is connected is a board
> design issue. Could the PHY interrupt be connected to the chip? Would
> the chip be able to wake the system? Should STMMAC_FLAG_USE_PHY_WOL be
> conditional?
>
> Andrew
>

Hi Andrew,

Yes, the PHY is doing the WoL. And I guess this makes sense as it allows
the MAC to power down during suspend to save power.

The INTN pin of QCA8081 is connected to the ETH_0_INT_N of QPS615. And
the INTN_WOL pin is connected to a SoC GPIO.

Without this change, I can't get WoL to work. I have a working branch
for our board here:
https://github.com/strongtz/linux-radxa-qcom/commits/v7.0.2-8280-wip/

--
Best regards,
Xilin Wu <sophon@radxa.com>