* [PATCH v2 0/8] drm/msm: add support for SM8450
@ 2022-11-02 23:13 Dmitry Baryshkov
2022-11-02 23:13 ` [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Change since v1:
- Fixed the regdma pointer in sm8450_dpu_cfg
- Rebased onto pending msm-next-lumag
- Added DT bindings for corresponding devices
Dmitry Baryshkov (8):
dt-bindings: display/msm/dsi-controller-main: allow defining opp-table
dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs
dt-bindings: display/msm: add support for the display on SM8450
drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
drm/msm/dsi: add support for DSI 2.6.0
drm/msm/dpu: add support for MDP_TOP blackhole
drm/msm/dpu: add support for SM8450
drm/msm: mdss add support for SM8450
.../display/msm/dsi-controller-main.yaml | 3 +
.../bindings/display/msm/dsi-phy-7nm.yaml | 2 +
.../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++
.../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++
drivers/gpu/drm/msm/Kconfig | 6 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 +++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +-
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++-
drivers/gpu/drm/msm/msm_mdss.c | 5 +
15 files changed, 864 insertions(+), 15 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
--
2.35.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-03 13:57 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov ` (6 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno Allow defining DSI OPP table inside the DSI controller node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 3b609c19e0bc..c37dd9503da0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -80,6 +80,9 @@ properties: operating-points-v2: true + opp-table: + type: object + ports: $ref: "/schemas/graph.yaml#/properties/ports" description: | -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table 2022-11-02 23:13 ` [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov @ 2022-11-03 13:57 ` Krzysztof Kozlowski 0 siblings, 0 replies; 17+ messages in thread From: Krzysztof Kozlowski @ 2022-11-03 13:57 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 02/11/2022 19:13, Dmitry Baryshkov wrote: > Allow defining DSI OPP table inside the DSI controller node. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-03 13:57 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov ` (5 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno SM8350 and SM8450 platforms use the same driver and same bindings as the existing 7nm DSI PHYs. Add corresponding compatibility strings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..bffd161fedfd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-5nm-8350 + - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs 2022-11-02 23:13 ` [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov @ 2022-11-03 13:57 ` Krzysztof Kozlowski 0 siblings, 0 replies; 17+ messages in thread From: Krzysztof Kozlowski @ 2022-11-03 13:57 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 02/11/2022 19:13, Dmitry Baryshkov wrote: > SM8350 and SM8450 platforms use the same driver and same bindings as the > existing 7nm DSI PHYs. Add corresponding compatibility strings. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-03 14:03 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov ` (4 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ 2 files changed, 481 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml new file mode 100644 index 000000000000..b8c508c50bc5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8450-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml new file mode 100644 index 000000000000..05c606e6ada3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -0,0 +1,349 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8450 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8450-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8450-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8450 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160310000{ + opp-hz = /bits/ 64 <160310000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-02 23:13 ` [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov @ 2022-11-03 14:03 ` Krzysztof Kozlowski 2022-11-04 12:34 ` Dmitry Baryshkov 2022-11-04 12:45 ` Dmitry Baryshkov 0 siblings, 2 replies; 17+ messages in thread From: Krzysztof Kozlowski @ 2022-11-03 14:03 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 02/11/2022 19:13, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ > 2 files changed, 481 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > new file mode 100644 > index 000000000000..b8c508c50bc5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display DPU > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# There is no such file and I could not fine any dependency mentioned in cover letter. I guess you miss link to your refactor series? This also means bot won't be able to test it... > + > +properties: > + compatible: > + const: qcom,sm8450-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display ahb clock > + - description: Display lut clock > + - description: Display core clock > + - description: Display vsync clock Drop "clock", less typing. > + > + clock-names: > + items: > + - const: bus > + - const: nrt_bus > + - const: iface > + - const: lut > + - const: core > + - const: vsync > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm8450.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sm8450.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@ae01000 { > + compatible = "qcom,sm8450-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-172000000{ > + opp-hz = /bits/ 64 <172000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > new file mode 100644 > index 000000000000..05c606e6ada3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > @@ -0,0 +1,349 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Drop "Device tree bindings for" and rewrite the sentence (e.g. drop "that"). > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree > + bindings of MDSS are mentioned for SM8450 target. Drop last sentence. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: Drop items. > + - const: qcom,sm8450-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display core clock Drop trailing "clocks" (the first "AHB clock" is ok) > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 You need specific names here. > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm8450-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-5nm-8450 > + > +unevaluatedProperties: false Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-03 14:03 ` Krzysztof Kozlowski @ 2022-11-04 12:34 ` Dmitry Baryshkov 2022-11-04 12:52 ` Krzysztof Kozlowski 2022-11-04 12:45 ` Dmitry Baryshkov 1 sibling, 1 reply; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 12:34 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 03/11/2022 17:03, Krzysztof Kozlowski wrote: > On 02/11/2022 19:13, Dmitry Baryshkov wrote: >> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm >> SM8450 platform. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ >> .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ >> 2 files changed, 481 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >> new file mode 100644 >> index 000000000000..b8c508c50bc5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >> @@ -0,0 +1,132 @@ >> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm SM8450 Display DPU >> + >> +maintainers: >> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> + >> +$ref: /schemas/display/msm/dpu-common.yaml# > > There is no such file and I could not fine any dependency mentioned in > cover letter. I guess you miss link to your refactor series? Excuse me, yes. However the refactoring should be already a part of linux-next, so I didn't think that I should especially point to it. > This also means bot won't be able to test it... How does bot detects the base commit? Should i use --base? Or does it work on top of linux-next? > >> + >> +properties: >> + compatible: >> + const: qcom,sm8450-dpu >> + >> + reg: >> + items: >> + - description: Address offset and size for mdp register set >> + - description: Address offset and size for vbif register set >> + >> + reg-names: >> + items: >> + - const: mdp >> + - const: vbif >> + >> + clocks: >> + items: >> + - description: Display hf axi clock >> + - description: Display sf axi clock >> + - description: Display ahb clock >> + - description: Display lut clock >> + - description: Display core clock >> + - description: Display vsync clock > > Drop "clock", less typing. Ack > >> + >> + clock-names: >> + items: >> + - const: bus >> + - const: nrt_bus >> + - const: iface >> + - const: lut >> + - const: core >> + - const: vsync >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> >> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/interconnect/qcom,sm8450.h> >> + #include <dt-bindings/power/qcom-rpmpd.h> >> + >> + display-controller@ae01000 { >> + compatible = "qcom,sm8450-dpu"; >> + reg = <0x0ae01000 0x8f000>, >> + <0x0aeb0000 0x2008>; >> + reg-names = "mdp", "vbif"; >> + >> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&gcc GCC_DISP_SF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + clock-names = "bus", >> + "nrt_bus", >> + "iface", >> + "lut", >> + "core", >> + "vsync"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmhpd SM8450_MMCX>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&dsi0_in>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpu_intf2_out: endpoint { >> + remote-endpoint = <&dsi1_in>; >> + }; >> + }; >> + }; >> + >> + mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-172000000{ >> + opp-hz = /bits/ 64 <172000000>; >> + required-opps = <&rpmhpd_opp_low_svs_d1>; >> + }; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-325000000 { >> + opp-hz = /bits/ 64 <325000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-375000000 { >> + opp-hz = /bits/ 64 <375000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-500000000 { >> + opp-hz = /bits/ 64 <500000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> +... >> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >> new file mode 100644 >> index 000000000000..05c606e6ada3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >> @@ -0,0 +1,349 @@ >> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm SM8450 Display MDSS >> + >> +maintainers: >> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> + >> +description: >> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > > Drop "Device tree bindings for" and rewrite the sentence (e.g. drop "that"). > >> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree >> + bindings of MDSS are mentioned for SM8450 target. > > Drop last sentence. > >> + >> +$ref: /schemas/display/msm/mdss-common.yaml# >> + >> +properties: >> + compatible: >> + items: > > Drop items. > >> + - const: qcom,sm8450-mdss > >> + >> + clocks: >> + items: >> + - description: Display AHB clock from gcc >> + - description: Display hf axi clock >> + - description: Display sf axi clock >> + - description: Display core clock > > Drop trailing "clocks" (the first "AHB clock" is ok) Hmm, not sure that I understand the difference, but fine with me. > >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: bus >> + - const: nrt_bus >> + - const: core >> + >> + iommus: >> + maxItems: 1 >> + >> + interconnects: >> + maxItems: 2 >> + >> + interconnect-names: >> + maxItems: 2 > > You need specific names here. Ack > >> + >> +patternProperties: >> + "^display-controller@[0-9a-f]+$": >> + type: object >> + properties: >> + compatible: >> + const: qcom,sm8450-dpu >> + >> + "^dsi@[0-9a-f]+$": >> + type: object >> + properties: >> + compatible: >> + const: qcom,mdss-dsi-ctrl >> + >> + "^phy@[0-9a-f]+$": >> + type: object >> + properties: >> + compatible: >> + const: qcom,dsi-phy-5nm-8450 >> + >> +unevaluatedProperties: false > > Best regards, > Krzysztof > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 12:34 ` Dmitry Baryshkov @ 2022-11-04 12:52 ` Krzysztof Kozlowski 2022-11-04 13:00 ` Dmitry Baryshkov 0 siblings, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2022-11-04 12:52 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 04/11/2022 08:34, Dmitry Baryshkov wrote: > On 03/11/2022 17:03, Krzysztof Kozlowski wrote: >> On 02/11/2022 19:13, Dmitry Baryshkov wrote: >>> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm >>> SM8450 platform. >>> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ >>> .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ >>> 2 files changed, 481 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>> new file mode 100644 >>> index 000000000000..b8c508c50bc5 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>> @@ -0,0 +1,132 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm SM8450 Display DPU >>> + >>> +maintainers: >>> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> + >>> +$ref: /schemas/display/msm/dpu-common.yaml# >> >> There is no such file and I could not fine any dependency mentioned in >> cover letter. I guess you miss link to your refactor series? > > Excuse me, yes. However the refactoring should be already a part of > linux-next, so I didn't think that I should especially point to it. Not in yesterday's next. > >> This also means bot won't be able to test it... > > How does bot detects the base commit? Should i use --base? Or does it > work on top of linux-next? I think bot tests on rc1, so even next would not help here. Anyway that's just a remark that you won't get automated test email. > >> >>> + >>> +properties: >>> + compatible: >>> + const: qcom,sm8450-dpu >>> + >>> + reg: >>> + items: >>> + - description: Address offset and size for mdp register set >>> + - description: Address offset and size for vbif register set >>> + >>> + reg-names: >>> + items: >>> + - const: mdp >>> + - const: vbif >>> + >>> + clocks: >>> + items: >>> + - description: Display hf axi clock >>> + - description: Display sf axi clock >>> + - description: Display ahb clock >>> + - description: Display lut clock >>> + - description: Display core clock >>> + - description: Display vsync clock >> >> Drop "clock", less typing. > > Ack > >> >>> + >>> + clock-names: >>> + items: >>> + - const: bus >>> + - const: nrt_bus >>> + - const: iface >>> + - const: lut >>> + - const: core >>> + - const: vsync >>> + >>> +unevaluatedProperties: false >>> + >>> +examples: >>> + - | >>> + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> >>> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> >>> + #include <dt-bindings/interrupt-controller/arm-gic.h> >>> + #include <dt-bindings/interconnect/qcom,sm8450.h> >>> + #include <dt-bindings/power/qcom-rpmpd.h> >>> + >>> + display-controller@ae01000 { >>> + compatible = "qcom,sm8450-dpu"; >>> + reg = <0x0ae01000 0x8f000>, >>> + <0x0aeb0000 0x2008>; >>> + reg-names = "mdp", "vbif"; >>> + >>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + clock-names = "bus", >>> + "nrt_bus", >>> + "iface", >>> + "lut", >>> + "core", >>> + "vsync"; >>> + >>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + assigned-clock-rates = <19200000>; >>> + >>> + operating-points-v2 = <&mdp_opp_table>; >>> + power-domains = <&rpmhpd SM8450_MMCX>; >>> + >>> + interrupt-parent = <&mdss>; >>> + interrupts = <0>; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + dpu_intf1_out: endpoint { >>> + remote-endpoint = <&dsi0_in>; >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + dpu_intf2_out: endpoint { >>> + remote-endpoint = <&dsi1_in>; >>> + }; >>> + }; >>> + }; >>> + >>> + mdp_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-172000000{ >>> + opp-hz = /bits/ 64 <172000000>; >>> + required-opps = <&rpmhpd_opp_low_svs_d1>; >>> + }; >>> + >>> + opp-200000000 { >>> + opp-hz = /bits/ 64 <200000000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-325000000 { >>> + opp-hz = /bits/ 64 <325000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-375000000 { >>> + opp-hz = /bits/ 64 <375000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + >>> + opp-500000000 { >>> + opp-hz = /bits/ 64 <500000000>; >>> + required-opps = <&rpmhpd_opp_nom>; >>> + }; >>> + }; >>> + }; >>> +... >>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>> new file mode 100644 >>> index 000000000000..05c606e6ada3 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>> @@ -0,0 +1,349 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm SM8450 Display MDSS >>> + >>> +maintainers: >>> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> + >>> +description: >>> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates >> >> Drop "Device tree bindings for" and rewrite the sentence (e.g. drop "that"). >> >>> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree >>> + bindings of MDSS are mentioned for SM8450 target. >> >> Drop last sentence. >> >>> + >>> +$ref: /schemas/display/msm/mdss-common.yaml# >>> + >>> +properties: >>> + compatible: >>> + items: >> >> Drop items. >> >>> + - const: qcom,sm8450-mdss >> >>> + >>> + clocks: >>> + items: >>> + - description: Display AHB clock from gcc >>> + - description: Display hf axi clock >>> + - description: Display sf axi clock >>> + - description: Display core clock >> >> Drop trailing "clocks" (the first "AHB clock" is ok) > > Hmm, not sure that I understand the difference, but fine with me. Not much different, but for me AHB is a bus, so "Display AHB from gcc" suggests a bit gcc provides some bus, but you want bus clock. AXI is also a bus... so maybe drop clock everywhere. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 12:52 ` Krzysztof Kozlowski @ 2022-11-04 13:00 ` Dmitry Baryshkov 0 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:00 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 04/11/2022 15:52, Krzysztof Kozlowski wrote: > On 04/11/2022 08:34, Dmitry Baryshkov wrote: >> On 03/11/2022 17:03, Krzysztof Kozlowski wrote: >>> On 02/11/2022 19:13, Dmitry Baryshkov wrote: >>>> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm >>>> SM8450 platform. >>>> >>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>> --- >>>> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ >>>> .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ >>>> 2 files changed, 481 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>>> new file mode 100644 >>>> index 000000000000..b8c508c50bc5 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>>> @@ -0,0 +1,132 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Qualcomm SM8450 Display DPU >>>> + >>>> +maintainers: >>>> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>> + >>>> +$ref: /schemas/display/msm/dpu-common.yaml# >>> >>> There is no such file and I could not fine any dependency mentioned in >>> cover letter. I guess you miss link to your refactor series? >> >> Excuse me, yes. However the refactoring should be already a part of >> linux-next, so I didn't think that I should especially point to it. > > Not in yesterday's next. > >> >>> This also means bot won't be able to test it... >> >> How does bot detects the base commit? Should i use --base? Or does it >> work on top of linux-next? > > I think bot tests on rc1, so even next would not help here. Anyway > that's just a remark that you won't get automated test email. > >> >>> >>>> + >>>> +properties: >>>> + compatible: >>>> + const: qcom,sm8450-dpu >>>> + >>>> + reg: >>>> + items: >>>> + - description: Address offset and size for mdp register set >>>> + - description: Address offset and size for vbif register set >>>> + >>>> + reg-names: >>>> + items: >>>> + - const: mdp >>>> + - const: vbif >>>> + >>>> + clocks: >>>> + items: >>>> + - description: Display hf axi clock >>>> + - description: Display sf axi clock >>>> + - description: Display ahb clock >>>> + - description: Display lut clock >>>> + - description: Display core clock >>>> + - description: Display vsync clock >>> >>> Drop "clock", less typing. >> >> Ack >> >>> >>>> + >>>> + clock-names: >>>> + items: >>>> + - const: bus >>>> + - const: nrt_bus >>>> + - const: iface >>>> + - const: lut >>>> + - const: core >>>> + - const: vsync >>>> + >>>> +unevaluatedProperties: false >>>> + >>>> +examples: >>>> + - | >>>> + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> >>>> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> >>>> + #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> + #include <dt-bindings/interconnect/qcom,sm8450.h> >>>> + #include <dt-bindings/power/qcom-rpmpd.h> >>>> + >>>> + display-controller@ae01000 { >>>> + compatible = "qcom,sm8450-dpu"; >>>> + reg = <0x0ae01000 0x8f000>, >>>> + <0x0aeb0000 0x2008>; >>>> + reg-names = "mdp", "vbif"; >>>> + >>>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >>>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >>>> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >>>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>>> + clock-names = "bus", >>>> + "nrt_bus", >>>> + "iface", >>>> + "lut", >>>> + "core", >>>> + "vsync"; >>>> + >>>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>>> + assigned-clock-rates = <19200000>; >>>> + >>>> + operating-points-v2 = <&mdp_opp_table>; >>>> + power-domains = <&rpmhpd SM8450_MMCX>; >>>> + >>>> + interrupt-parent = <&mdss>; >>>> + interrupts = <0>; >>>> + >>>> + ports { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + >>>> + port@0 { >>>> + reg = <0>; >>>> + dpu_intf1_out: endpoint { >>>> + remote-endpoint = <&dsi0_in>; >>>> + }; >>>> + }; >>>> + >>>> + port@1 { >>>> + reg = <1>; >>>> + dpu_intf2_out: endpoint { >>>> + remote-endpoint = <&dsi1_in>; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + mdp_opp_table: opp-table { >>>> + compatible = "operating-points-v2"; >>>> + >>>> + opp-172000000{ >>>> + opp-hz = /bits/ 64 <172000000>; >>>> + required-opps = <&rpmhpd_opp_low_svs_d1>; >>>> + }; >>>> + >>>> + opp-200000000 { >>>> + opp-hz = /bits/ 64 <200000000>; >>>> + required-opps = <&rpmhpd_opp_low_svs>; >>>> + }; >>>> + >>>> + opp-325000000 { >>>> + opp-hz = /bits/ 64 <325000000>; >>>> + required-opps = <&rpmhpd_opp_svs>; >>>> + }; >>>> + >>>> + opp-375000000 { >>>> + opp-hz = /bits/ 64 <375000000>; >>>> + required-opps = <&rpmhpd_opp_svs_l1>; >>>> + }; >>>> + >>>> + opp-500000000 { >>>> + opp-hz = /bits/ 64 <500000000>; >>>> + required-opps = <&rpmhpd_opp_nom>; >>>> + }; >>>> + }; >>>> + }; >>>> +... >>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>>> new file mode 100644 >>>> index 000000000000..05c606e6ada3 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>>> @@ -0,0 +1,349 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Qualcomm SM8450 Display MDSS >>>> + >>>> +maintainers: >>>> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>> + >>>> +description: >>>> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates >>> >>> Drop "Device tree bindings for" and rewrite the sentence (e.g. drop "that"). >>> >>>> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree >>>> + bindings of MDSS are mentioned for SM8450 target. >>> >>> Drop last sentence. >>> >>>> + >>>> +$ref: /schemas/display/msm/mdss-common.yaml# >>>> + >>>> +properties: >>>> + compatible: >>>> + items: >>> >>> Drop items. >>> >>>> + - const: qcom,sm8450-mdss >>> >>>> + >>>> + clocks: >>>> + items: >>>> + - description: Display AHB clock from gcc >>>> + - description: Display hf axi clock >>>> + - description: Display sf axi clock >>>> + - description: Display core clock >>> >>> Drop trailing "clocks" (the first "AHB clock" is ok) >> >> Hmm, not sure that I understand the difference, but fine with me. > > Not much different, but for me AHB is a bus, so "Display AHB from gcc" > suggests a bit gcc provides some bus, but you want bus clock. AXI is > also a bus... so maybe drop clock everywhere. Ack. Sounds logical. And the 'from gcc' too. -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-03 14:03 ` Krzysztof Kozlowski 2022-11-04 12:34 ` Dmitry Baryshkov @ 2022-11-04 12:45 ` Dmitry Baryshkov 2022-11-04 13:09 ` Krzysztof Kozlowski 1 sibling, 1 reply; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 12:45 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 03/11/2022 17:03, Krzysztof Kozlowski wrote: > On 02/11/2022 19:13, Dmitry Baryshkov wrote: >> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm >> SM8450 platform. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ >> .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ >> 2 files changed, 481 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >> [skipped] >> + >> +$ref: /schemas/display/msm/mdss-common.yaml# >> + >> +properties: >> + compatible: >> + items: [skipped] >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: bus >> + - const: nrt_bus >> + - const: core >> + >> + iommus: >> + maxItems: 1 >> + >> + interconnects: >> + maxItems: 2 >> + >> + interconnect-names: >> + maxItems: 2 > > You need specific names here. > The names are described in mdss-common.yaml -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 12:45 ` Dmitry Baryshkov @ 2022-11-04 13:09 ` Krzysztof Kozlowski 0 siblings, 0 replies; 17+ messages in thread From: Krzysztof Kozlowski @ 2022-11-04 13:09 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 04/11/2022 08:45, Dmitry Baryshkov wrote: > On 03/11/2022 17:03, Krzysztof Kozlowski wrote: >> On 02/11/2022 19:13, Dmitry Baryshkov wrote: >>> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm >>> SM8450 platform. >>> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ >>> .../display/msm/qcom,sm8450-mdss.yaml | 349 ++++++++++++++++++ >>> 2 files changed, 481 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml >>> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml >>> > > [skipped] > >>> + >>> +$ref: /schemas/display/msm/mdss-common.yaml# >>> + >>> +properties: >>> + compatible: >>> + items: > > [skipped] > >>> + >>> + clock-names: >>> + items: >>> + - const: iface >>> + - const: bus >>> + - const: nrt_bus >>> + - const: core >>> + >>> + iommus: >>> + maxItems: 1 >>> + >>> + interconnects: >>> + maxItems: 2 >>> + >>> + interconnect-names: >>> + maxItems: 2 >> >> You need specific names here. >> > > The names are described in mdss-common.yaml Ah, then it is ok. I could not check these :/ Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov ` (2 preceding siblings ...) 2022-11-02 23:13 ` [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 5/8] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov ` (3 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Robert Foss, Vinod Koul SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm variants inside the common 5+7nm driver. Co-developed-by: Robert Foss <robert.foss@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/Kconfig | 6 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++++++++++++-- 4 files changed, 131 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 3c9dfdb0b328..e7b100d97f88 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY Choose this option if DSI PHY on SDM845 is used on the platform. config DRM_MSM_DSI_7NM_PHY - bool "Enable DSI 7nm PHY driver in MSM DRM" + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" depends on DRM_MSM_DSI default y help - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on - the platform. + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 + is used on the platform. config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ee6051367679..0c956fdab23e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_7nm_8150_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8350", + .data = &dsi_phy_5nm_8350_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8450", + .data = &dsi_phy_5nm_8450_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 1096afedd616..f7a907ed2b4b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 9e7fa7d88ead..1696ff150b9e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -39,8 +39,14 @@ #define VCO_REF_CLK_RATE 19200000 #define FRAC_BITS 18 +/* Hardware is pre V4.1 */ +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) /* Hardware is V4.1 */ -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) +/* Hardware is V4.2 */ +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) +/* Hardware is V4.3 */ +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) struct dsi_pll_config { bool enable_ssc; @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config dec_multiple = div_u64(pll_freq * multiplier, divider); dec = div_u64_rem(dec_multiple, multiplier, &frac); - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) config->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) config->pll_clock_inverters = 0xa0; @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->phy->pll_base; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate < 1520000000ULL) vco_config_1 = 0x08; else if (pll->vco_current_rate < 2990000000ULL) vco_config_1 = 0x01; } + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { + if (pll->vco_current_rate < 1520000000ULL) + vco_config_1 = 0x08; + else if (pll->vco_current_rate >= 2990000000ULL) + vco_config_1 = 0x01; + } + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, analog_controls_five_1); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) const u8 *tx_dctrl = tx_dctrl_0; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) tx_dctrl = tx_dctrl_1; /* Strength ctrl settings */ @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, if (dsi_phy_hw_v4_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); + /* Request for REFGEN READY */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); + udelay(500); + } + /* wait for REFGEN READY */ ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, status, (status & BIT(0)), @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, } if (phy->cphy_mode) { - vreg_ctrl_0 = 0x51; vreg_ctrl_1 = 0x55; glbl_pemph_ctrl_0 = 0x11; lane_ctrl0 = 0x17; @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) pr_warn("Turning OFF PHY while PLL is on\n"); dsi_phy_hw_v4_0_config_lpcdrx(phy, false); + + /* Turn off REFGEN Vote */ + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); + wmb(); + /* Delay to ensure HW removes vote before PHY shut down */ + udelay(2); + data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); /* disable all lanes */ @@ -1079,6 +1136,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, }; const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { @@ -1102,3 +1160,57 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { .num_dsi_phy = 1, .quirks = DSI_PHY_7NM_QUIRK_V4_1, }; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { + .has_phy_lane = true, + .reg_cfg = { + .num = 1, + .regs = { + {"vdds", 37550, 0}, + }, + }, + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { + .has_phy_lane = true, + .reg_cfg = { + .num = 1, + .regs = { + {"vdds", 97800, 0}, + }, + }, + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_3, +}; -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 5/8] drm/msm/dsi: add support for DSI 2.6.0 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov ` (3 preceding siblings ...) 2022-11-02 23:13 ` [PATCH v2 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 6/8] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov ` (2 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add support for DSI 2.6.0 (block used on sm8450). Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 7e97c239ed48..59a4cc95a251 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, }; const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 8f04e685a74e..95957fab499d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_V2_VER_MINOR_8064 0x0 -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov ` (4 preceding siblings ...) 2022-11-02 23:13 ` [PATCH v2 5/8] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 7/8] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 8/8] drm/msm: mdss " Dmitry Baryshkov 7 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On sm8450 a register block was removed from MDP TOP. Accessing it during snapshotting results in NoC errors / immediate reboot. Skip accessing these registers during snapshot. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 38aa38ab1568..4730f8268f2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -92,6 +92,7 @@ enum { DPU_MDP_UBWC_1_0, DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, + DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index f3660cd14f4f..67f2e5288b3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, - dpu_kms->mmio + cat->mdp[0].base, "top"); + if (top->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + msm_disp_snapshot_add_block(disp_state, 0x380, + dpu_kms->mmio + cat->mdp[0].base, "top"); + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); + } else { + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, + dpu_kms->mmio + cat->mdp[0].base, "top"); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 7/8] drm/msm/dpu: add support for SM8450 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov ` (5 preceding siblings ...) 2022-11-02 23:13 ` [PATCH v2 6/8] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 8/8] drm/msm: mdss " Dmitry Baryshkov 7 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add definitions for the display hardware used on Qualcomm SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 229 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index bae3cc3adb3f..3149966d2c65 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -124,6 +124,15 @@ BIT(MDP_AD4_0_INTR) | \ BIT(MDP_AD4_1_INTR)) +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + 0) + #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_caps sm8450_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version = DPU_HW_UBWC_VER_40, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { }, }; +static const struct dpu_mdp_cfg sm8450_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { + .reg_off = 0x2B4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { + .reg_off = 0x2BC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { + .reg_off = 0x2C4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x2BC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x2C4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { + .reg_off = 0x2BC, .bit_off = 20}, + }, +}; + static const struct dpu_mdp_cfg sc7280_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { }, }; +static const struct dpu_ctl_cfg sm8450_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg sc7280_ctl[] = { { .name = "ctl_0", .id = CTL_0, @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + +static const struct dpu_sspp_cfg sm8450_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg sc7280_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -1184,6 +1301,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), }; +/* FIXME: interrupts */ +static const struct dpu_pingpong_cfg sm8450_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), +}; + /************************************************************* * MERGE_3D sub blocks config *************************************************************/ @@ -1201,6 +1346,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), +}; + static const struct dpu_pingpong_cfg sc7280_pp[] = { PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), }; +static const struct dpu_intf_cfg sm8450_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + /************************************************************* * Writeback blocks config *************************************************************/ @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { .clk_ctrl = DPU_CLK_CTRL_REG_DMA, }; +static const struct dpu_reg_dma_cfg sm8450_regdma = { + .base = 0x0, + .version = 0x00020000, + .trigger_sel_off = 0x119c, + .xin_id = 7, + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, +}; + /************************************************************* * PERF data config *************************************************************/ @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_perf_cfg sm8450_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + static const struct dpu_perf_cfg sc7280_perf_data = { .max_bw_low = 4700000, .max_bw_high = 8800000, @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { .mdss_irqs = IRQ_SM8250_MASK, }; +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { + .caps = &sm8450_dpu_caps, + .mdp_count = ARRAY_SIZE(sm8450_mdp), + .mdp = sm8450_mdp, + .ctl_count = ARRAY_SIZE(sm8450_ctl), + .ctl = sm8450_ctl, + .sspp_count = ARRAY_SIZE(sm8450_sspp), + .sspp = sm8450_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .pingpong_count = ARRAY_SIZE(sm8450_pp), + .pingpong = sm8450_pp, + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), + .merge_3d = sm8450_merge_3d, + .intf_count = ARRAY_SIZE(sm8450_intf), + .intf = sm8450_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8450_regdma, + .perf = &sm8450_perf_data, + .mdss_irqs = IRQ_SM8450_MASK, +}; + static const struct dpu_mdss_cfg sc7280_dpu_cfg = { .caps = &sc7280_dpu_caps, .mdp_count = ARRAY_SIZE(sc7280_mdp), @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, }; const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4730f8268f2a..4526ef71c326 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -46,6 +46,7 @@ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -195,6 +195,8 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, + PINGPONG_6, + PINGPONG_7, PINGPONG_S0, PINGPONG_MAX }; @@ -203,6 +205,7 @@ enum dpu_merge_3d { MERGE_3D_0 = 1, MERGE_3D_1, MERGE_3D_2, + MERGE_3D_3, MERGE_3D_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 67f2e5288b3c..109b08ded269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8180x-dpu", }, { .compatible = "qcom,sm8150-dpu", }, { .compatible = "qcom,sm8250-dpu", }, + { .compatible = "qcom,sm8450-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 8/8] drm/msm: mdss add support for SM8450 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov ` (6 preceding siblings ...) 2022-11-02 23:13 ` [PATCH v2 7/8] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov @ 2022-11-02 23:13 ` Dmitry Baryshkov 7 siblings, 0 replies; 17+ messages in thread From: Dmitry Baryshkov @ 2022-11-02 23:13 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add support for the MDSS block on SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 6a4549ef34d4..5602fbaf6e0e 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; + case DPU_HW_VER_810: + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); + break; } return ret; @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8450-mdss" }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-11-04 13:09 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-11-02 23:13 [PATCH v2 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov 2022-11-03 13:57 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov 2022-11-03 13:57 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 3/8] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov 2022-11-03 14:03 ` Krzysztof Kozlowski 2022-11-04 12:34 ` Dmitry Baryshkov 2022-11-04 12:52 ` Krzysztof Kozlowski 2022-11-04 13:00 ` Dmitry Baryshkov 2022-11-04 12:45 ` Dmitry Baryshkov 2022-11-04 13:09 ` Krzysztof Kozlowski 2022-11-02 23:13 ` [PATCH v2 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 5/8] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 6/8] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 7/8] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov 2022-11-02 23:13 ` [PATCH v2 8/8] drm/msm: mdss " Dmitry Baryshkov
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