[PATCH 0/3] Patches used to add platform specific data for Intel Stratix10 platform

[PATCH 0/3] Patches used to add platform specific data for Intel Stratix10 platform

[Meng Li]

*** BLURB HERE ***

Meng Li (3):
  usb: dwc2: Add platform specific data for Intel Stratix10 platform
  arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
  dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

 Documentation/devicetree/bindings/usb/dwc2.yaml   | 1 +
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 drivers/usb/dwc2/params.c                         | 2 ++
 3 files changed, 5 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10 platform

[Meng Li]

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. So, refer to
commit 3d8d3504d233("usb: dwc2: Add platform specific data for
Intel's Agilex"), add platform specific data for Intel Stratix10 platform.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 8eab5f38b110..3d085ae1ecd8 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
 	  .data = dwc2_set_stm32mp15_hsotg_params },
 	{ .compatible = "intel,socfpga-agilex-hsotg",
 	  .data = dwc2_set_socfpga_agilex_params },
+	{ .compatible = "intel,socfpga-stratix10-hsotg",
+	  .data = dwc2_set_socfpga_agilex_params },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
-- 
2.34.1

Re: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10 platform

[Krzysztof Kozlowski]

On 19/07/2023 04:55, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. So, refer to
> commit 3d8d3504d233("usb: dwc2: Add platform specific data for
> Intel's Agilex"), add platform specific data for Intel Stratix10 platform.
> 
> Signed-off-by: Meng Li <Meng.Li@windriver.com>
> ---
>  drivers/usb/dwc2/params.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 8eab5f38b110..3d085ae1ecd8 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
>  	  .data = dwc2_set_stm32mp15_hsotg_params },
>  	{ .compatible = "intel,socfpga-agilex-hsotg",
>  	  .data = dwc2_set_socfpga_agilex_params },
> +	{ .compatible = "intel,socfpga-stratix10-hsotg",
> +	  .data = dwc2_set_socfpga_agilex_params },

NAK. I already wrote why.

Best regards,
Krzysztof

RE: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10 platform

[Li, Meng]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, July 19, 2023 2:40 PM
> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10
> platform
> 
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
> 
> On 19/07/2023 04:55, Meng Li wrote:
> > Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> > the Stratix platform also does not support clock-gating. So, refer to
> > commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
> > Agilex"), add platform specific data for Intel Stratix10 platform.
> >
> > Signed-off-by: Meng Li <Meng.Li@windriver.com>
> > ---
> >  drivers/usb/dwc2/params.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> > index 8eab5f38b110..3d085ae1ecd8 100644
> > --- a/drivers/usb/dwc2/params.c
> > +++ b/drivers/usb/dwc2/params.c
> > @@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
> >         .data = dwc2_set_stm32mp15_hsotg_params },
> >       { .compatible = "intel,socfpga-agilex-hsotg",
> >         .data = dwc2_set_socfpga_agilex_params },
> > +     { .compatible = "intel,socfpga-stratix10-hsotg",
> > +       .data = dwc2_set_socfpga_agilex_params },
> 
> NAK. I already wrote why.

If I don't add the SoC specific compatible entry, how I use to the specific data on Stratix10 platform.
If you think the new SoC specific compatible entry is not necessary, the patch2 also has issue.

Thanks,
Limeng

> 
> Best regards,
> Krzysztof

Re: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10 platform

[Krzysztof Kozlowski]

On 19/07/2023 11:10, Li, Meng wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Wednesday, July 19, 2023 2:40 PM
>> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
>> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
>> devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 1/3] usb: dwc2: Add platform specific data for Intel Stratix10
>> platform
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 19/07/2023 04:55, Meng Li wrote:
>>> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
>>> the Stratix platform also does not support clock-gating. So, refer to
>>> commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
>>> Agilex"), add platform specific data for Intel Stratix10 platform.
>>>
>>> Signed-off-by: Meng Li <Meng.Li@windriver.com>
>>> ---
>>>  drivers/usb/dwc2/params.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
>>> index 8eab5f38b110..3d085ae1ecd8 100644
>>> --- a/drivers/usb/dwc2/params.c
>>> +++ b/drivers/usb/dwc2/params.c
>>> @@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
>>>         .data = dwc2_set_stm32mp15_hsotg_params },
>>>       { .compatible = "intel,socfpga-agilex-hsotg",
>>>         .data = dwc2_set_socfpga_agilex_params },
>>> +     { .compatible = "intel,socfpga-stratix10-hsotg",
>>> +       .data = dwc2_set_socfpga_agilex_params },
>>
>> NAK. I already wrote why.
> 
> If I don't add the SoC specific compatible entry, how I use to the specific data on Stratix10 platform.

You do not have match data specific to Stratix10. I explained already
that I expect them to be compatible. I gave you example how it is done.
What is unclear in that example?

> If you think the new SoC specific compatible entry is not necessary, the patch2 also has issue.


Best regards,
Krzysztof

[PATCH 2/3] arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

[Meng Li]

The DWC2 USB controller on the Stratix10 platform does not support
clock gating, so use the chip specific "intel,socfpga-stratix10-hsotg"
compatible.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index ea788a920eab..435f1cc52af3 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
 		};
 
 		usb0: usb@ffb00000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-stratix10-hsotg", "snps,dwc2";
 			reg = <0xffb00000 0x40000>;
 			interrupts = <0 93 4>;
 			phys = <&usbphy0>;
@@ -504,7 +504,7 @@ usb0: usb@ffb00000 {
 		};
 
 		usb1: usb@ffb40000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-stratix10-hsotg", "snps,dwc2";
 			reg = <0xffb40000 0x40000>;
 			interrupts = <0 94 4>;
 			phys = <&usbphy0>;
-- 
2.34.1

[PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Meng Li]

Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
implementation, because the Stratix DWC2 implementation does
not support clock gating. This compatible is used with generic
snps,dwc2.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
---
 Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index dc4988c0009c..f90094320914 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -51,6 +51,7 @@ properties:
               - amlogic,meson-g12a-usb
               - amlogic,meson-a1-usb
               - intel,socfpga-agilex-hsotg
+              - intel,socfpga-stratix10-hsotg
           - const: snps,dwc2
       - const: amcc,dwc-otg
       - const: apm,apm82181-dwc-otg
-- 
2.34.1

Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Krzysztof Kozlowski]

On 19/07/2023 04:55, Meng Li wrote:
> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> implementation, because the Stratix DWC2 implementation does
> not support clock gating. This compatible is used with generic
> snps,dwc2.
> 
> Signed-off-by: Meng Li <Meng.Li@windriver.com>

Missing changelog, missing versioning. This is v3 or v4.

> ---
>  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
> index dc4988c0009c..f90094320914 100644
> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> @@ -51,6 +51,7 @@ properties:
>                - amlogic,meson-g12a-usb
>                - amlogic,meson-a1-usb
>                - intel,socfpga-agilex-hsotg
> +              - intel,socfpga-stratix10-hsotg

So you just sent the same patch as before. I pointed you to the proper
solution with compatibility.



Best regards,
Krzysztof

RE: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Li, Meng]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, July 19, 2023 2:39 PM
> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
> stratix10-hsotg"
> 
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
> 
> On 19/07/2023 04:55, Meng Li wrote:
> > Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> > implementation, because the Stratix DWC2 implementation does not
> > support clock gating. This compatible is used with generic snps,dwc2.
> >
> > Signed-off-by: Meng Li <Meng.Li@windriver.com>
> 
> Missing changelog, missing versioning. This is v3 or v4.
> 
> > ---
> >  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
> > b/Documentation/devicetree/bindings/usb/dwc2.yaml
> > index dc4988c0009c..f90094320914 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> > +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> > @@ -51,6 +51,7 @@ properties:
> >                - amlogic,meson-g12a-usb
> >                - amlogic,meson-a1-usb
> >                - intel,socfpga-agilex-hsotg
> > +              - intel,socfpga-stratix10-hsotg
> 
> So you just sent the same patch as before. I pointed you to the proper solution
> with compatibility.
> 

No. not the same.
I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg" is not allowed.

You said "Where is SoC specific compatible?"
Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but why it is still not reasonable.

Thanks,
Limeng

> 
> 
> Best regards,
> Krzysztof

Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Krzysztof Kozlowski]

On 19/07/2023 10:45, Li, Meng wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Wednesday, July 19, 2023 2:39 PM
>> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
>> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
>> devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
>> stratix10-hsotg"
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 19/07/2023 04:55, Meng Li wrote:
>>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
>>> implementation, because the Stratix DWC2 implementation does not
>>> support clock gating. This compatible is used with generic snps,dwc2.
>>>
>>> Signed-off-by: Meng Li <Meng.Li@windriver.com>
>>
>> Missing changelog, missing versioning. This is v3 or v4.
>>
>>> ---
>>>  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> index dc4988c0009c..f90094320914 100644
>>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> @@ -51,6 +51,7 @@ properties:
>>>                - amlogic,meson-g12a-usb
>>>                - amlogic,meson-a1-usb
>>>                - intel,socfpga-agilex-hsotg
>>> +              - intel,socfpga-stratix10-hsotg
>>
>> So you just sent the same patch as before. I pointed you to the proper solution
>> with compatibility.
>>
> 
> No. not the same.
> I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg" is not allowed.
> 
> You said "Where is SoC specific compatible?"
> Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but why it is still not reasonable.

The compatible should be added, but I said they are compatible, so
express it. I also gave you example of file which expresses it.

Why that compatible is not allowed alone? Because what we said here
many, many times and because the doc I gave you which explains this.

Best regards,
Krzysztof

RE: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Li, Meng]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, July 19, 2023 4:59 PM
> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
> stratix10-hsotg"
> 
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
> 
> On 19/07/2023 10:45, Li, Meng wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> Sent: Wednesday, July 19, 2023 2:39 PM
> >> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
> >> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> >> robh+conor+dt@kernel.org;
> >> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
> >> devicetree@vger.kernel.org
> >> Cc: linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible
> >> "intel,socfpga- stratix10-hsotg"
> >>
> >> CAUTION: This email comes from a non Wind River email account!
> >> Do not click links or open attachments unless you recognize the
> >> sender and know the content is safe.
> >>
> >> On 19/07/2023 04:55, Meng Li wrote:
> >>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> >>> implementation, because the Stratix DWC2 implementation does not
> >>> support clock gating. This compatible is used with generic snps,dwc2.
> >>>
> >>> Signed-off-by: Meng Li <Meng.Li@windriver.com>
> >>
> >> Missing changelog, missing versioning. This is v3 or v4.
> >>
> >>> ---
> >>>  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
> >>>  1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> index dc4988c0009c..f90094320914 100644
> >>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> @@ -51,6 +51,7 @@ properties:
> >>>                - amlogic,meson-g12a-usb
> >>>                - amlogic,meson-a1-usb
> >>>                - intel,socfpga-agilex-hsotg
> >>> +              - intel,socfpga-stratix10-hsotg
> >>
> >> So you just sent the same patch as before. I pointed you to the
> >> proper solution with compatibility.
> >>
> >
> > No. not the same.
> > I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is
> able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg"
> is not allowed.
> >
> > You said "Where is SoC specific compatible?"
> > Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but
> why it is still not reasonable.
> 
> The compatible should be added, but I said they are compatible, so express it. I
> also gave you example of file which expresses it.
> 
> Why that compatible is not allowed alone? Because what we said here many,
> many times and because the doc I gave you which explains this.
> 

I had a look the doc ,and refer to rk3128.dtsi and commit 5032b269203287c17064d33c72be1ebf30c04a95.
So I think it needs to add " intel,socfpga-stratix10-hsotg" Documentation/devicetree/bindings/usb/dwc2.yaml.
But if you think it is not reasonable, could you please show what is your modification for the dwc2.yaml.

Thanks,
Limeng


> Best regards,
> Krzysztof

Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-stratix10-hsotg"

[Krzysztof Kozlowski]

On 19/07/2023 11:49, Li, Meng wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Wednesday, July 19, 2023 4:59 PM
>> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
>> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
>> devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
>> stratix10-hsotg"
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 19/07/2023 10:45, Li, Meng wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> Sent: Wednesday, July 19, 2023 2:39 PM
>>>> To: Li, Meng <Meng.Li@windriver.com>; gregkh@linuxfoundation.org;
>>>> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
>>>> robh+conor+dt@kernel.org;
>>>> dinguyen@kernel.org; hminas@synopsys.com; linux-usb@vger.kernel.org;
>>>> devicetree@vger.kernel.org
>>>> Cc: linux-kernel@vger.kernel.org
>>>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible
>>>> "intel,socfpga- stratix10-hsotg"
>>>>
>>>> CAUTION: This email comes from a non Wind River email account!
>>>> Do not click links or open attachments unless you recognize the
>>>> sender and know the content is safe.
>>>>
>>>> On 19/07/2023 04:55, Meng Li wrote:
>>>>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
>>>>> implementation, because the Stratix DWC2 implementation does not
>>>>> support clock gating. This compatible is used with generic snps,dwc2.
>>>>>
>>>>> Signed-off-by: Meng Li <Meng.Li@windriver.com>
>>>>
>>>> Missing changelog, missing versioning. This is v3 or v4.
>>>>
>>>>> ---
>>>>>  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>>>>>  1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> index dc4988c0009c..f90094320914 100644
>>>>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> @@ -51,6 +51,7 @@ properties:
>>>>>                - amlogic,meson-g12a-usb
>>>>>                - amlogic,meson-a1-usb
>>>>>                - intel,socfpga-agilex-hsotg
>>>>> +              - intel,socfpga-stratix10-hsotg
>>>>
>>>> So you just sent the same patch as before. I pointed you to the
>>>> proper solution with compatibility.
>>>>
>>>
>>> No. not the same.
>>> I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is
>> able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg"
>> is not allowed.
>>>
>>> You said "Where is SoC specific compatible?"
>>> Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but
>> why it is still not reasonable.
>>
>> The compatible should be added, but I said they are compatible, so express it. I
>> also gave you example of file which expresses it.
>>
>> Why that compatible is not allowed alone? Because what we said here many,
>> many times and because the doc I gave you which explains this.
>>
> 
> I had a look the doc ,and refer to rk3128.dtsi and commit 5032b269203287c17064d33c72be1ebf30c04a95.
> So I think it needs to add " intel,socfpga-stratix10-hsotg" Documentation/devicetree/bindings/usb/dwc2.yaml.

Open the DTSI and look at compatibles. Now open the driver and look at
the compatibles - surprise, there is no rockchip,rk3128-usb! Now open
the binding and look how it is done.

> But if you think it is not reasonable, could you please show what is your modification for the dwc2.yaml.

Open the binding - it is already there.

I bet there is someone in Windriver who does Linux and can help here as
well, none of existing code is working for you as an example?

Best regards,
Krzysztof