[PATCH v5 0/4] arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar + add overlay tests

[PATCH v5 0/4] arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar + add overlay tests

[Quentin Schulz]

This adds minimal support for the Pre-ICT tester adapter for RK3588
Jaguar.
GPIO3A3, GPIO3A4, GPIO3B2 and GPIO3D2 to GPIO3D5 are all routed to power
rails and can only be used as input and their bias are important to be
able to properly detect soldering issues.

Additionally, this adds build-time overlay application tests for all
Rockchip overlays to try to avoid future regressions.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes in v5:
- re-add dtb-$(CONFIG_ARCH_ROCKCHIP) += *.dtbo so that an explicit rule
  exists and we don't rely on the overlay tests to generate the dtbo,
- reword comment on overlay tests by making it explicit that we require
  both an overlay test and an explicit build target for the dtbo,
- Link to v4: https://lore.kernel.org/r/20250131-pre-ict-jaguar-v4-0-c971e2852e8d@cherry.de

Changes in v4:
- fix typos in WolfVision patch,
- added Rb on WolfVision patch,
- Link to v3: https://lore.kernel.org/r/20250128-pre-ict-jaguar-v3-0-7be2f09d390a@cherry.de

Changes in v3:
- removed Fixes tag and intent to send to stable as this patch almost
  doubles the size of the main DTB. Let's not potentially break users of
  stable releases,
- added Wolfvision PF5 overlay tests, thanks Michael,
- added comment on how to add new overlays (via tests), and the side
  effects,
- grouped the overlay application test target with the definition of its
  dependencies (DTB + DTBO(s)),
- added trailers,
- Link to v2: https://lore.kernel.org/r/20250116-pre-ict-jaguar-v2-0-157d319004fc@cherry.de

Changes in v2:
- add overlay application tests for Edgeble NCM6A WiFi and Rock 5B PCIe
  Endpoint+SNRS
- add overlay application test for RK3588 Jaguar + Pre-ICT tester
  adapter,
- Link to v1: https://lore.kernel.org/r/20241206-pre-ict-jaguar-v1-1-7f660bd4b70c@cherry.de

---
Quentin Schulz (4):
      arm64: dts: rockchip: add overlay test for WolfVision PF5
      arm64: dts: rockchip: add overlay test for Edgeble NCM6A
      arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlays
      arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar

 arch/arm64/boot/dts/rockchip/Makefile              |  39 +++++
 .../dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso | 171 +++++++++++++++++++++
 2 files changed, 210 insertions(+)
---
base-commit: bb066fe812d6fb3a9d01c073d9f1e2fd5a63403b
change-id: 20241206-pre-ict-jaguar-b90fafee8bd8

Best regards,
-- 
Quentin Schulz <quentin.schulz@cherry.de>

[PATCH v5 1/4] arm64: dts: rockchip: add overlay test for WolfVision PF5

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO Expander
board connected to it. Therefore, let's generate an overlay test so the
application of the two overlays are validated against the base DTB.

Suggested-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 arch/arm64/boot/dts/rockchip/Makefile | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index def1222c1907eb16b23cff6d540174a4e897abc9..534e70a649eeada7f9b6f12596b83f5c47b184b4 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -170,3 +170,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
+
+# Overlay application tests
+#
+# A .dtbo must have its own
+#
+#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo
+#
+# entry, and at least one overlay application test - ideally reflecting how it
+# will be used in real life -:
+#
+#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <name of overlay application test>.dtb
+#  <name of overlay application test>-dtbs := <base>.dtb <overlay-1>.dtbo [<overlay-2>.dtbo ...]
+#
+# This will make the <base>.dtb have symbols (like when DTC_FLAGS has -@ passed)
+# and generate a new DTB (<name of overlay application test>.dtb) which is the
+# result of the application of <overlay-1>.dtbo and other listed overlays on top
+# of <base>.dtb.
+
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
+rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
+	rk3568-wolfvision-pf5-display-vz.dtbo \
+	rk3568-wolfvision-pf5-io-expander.dtbo

-- 
2.48.1

Re: [PATCH v5 1/4] arm64: dts: rockchip: add overlay test for WolfVision PF5

[Dragan Simic]

Hello Quentin,

Please see a few comments below.

On 2025-02-07 16:19, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO 
> Expander
> board connected to it. Therefore, let's generate an overlay test so the
> application of the two overlays are validated against the base DTB.
> 
> Suggested-by: Michael Riesch <michael.riesch@wolfvision.net>
> Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> 
> ---
>  arch/arm64/boot/dts/rockchip/Makefile | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
> b/arch/arm64/boot/dts/rockchip/Makefile
> index
> def1222c1907eb16b23cff6d540174a4e897abc9..534e70a649eeada7f9b6f12596b83f5c47b184b4
> 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -170,3 +170,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += 
> rk3588s-orangepi-5.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
> +
> +# Overlay application tests
> +#
> +# A .dtbo must have its own
> +#
> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo
> +#
> +# entry, and at least one overlay application test - ideally 
> reflecting how it
> +# will be used in real life -:

Hmm, what's "-:" actually doing in the line right above?  I mean,
it's a minor nitpick, so might be worth addressing only if there
will be the v6...  Also, "test - ideally" might be replaced by
"test, ideally", because splicing sentences together using em/en
dashes is generally frowned upon. :)

> +#
> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <name of overlay application 
> test>.dtb
> +#  <name of overlay application test>-dtbs := <base>.dtb
> <overlay-1>.dtbo [<overlay-2>.dtbo ...]

As another minor nitpick, I'd suggest that

     "<name of overlay application test>.dtb"

is replaced with

     "<name-of-overlay-application-test>.dtb"

for the sake of consistency and, obviously, for clear indication of
the space characters not being applicable.  Regarding using "-" or "_"
characters there, perhaps we should follow what Git uses in its man
pages, which is the "-" character (see e.g. git-switch(1)).

> +#
> +# This will make the <base>.dtb have symbols (like when DTC_FLAGS has
> -@ passed)
> +# and generate a new DTB (<name of overlay application test>.dtb) 
> which is the
> +# result of the application of <overlay-1>.dtbo and other listed
> overlays on top
> +# of <base>.dtb.
> +
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
> +rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
> +	rk3568-wolfvision-pf5-display-vz.dtbo \
> +	rk3568-wolfvision-pf5-io-expander.dtbo

Otherwise, it's looking good to me, thanks for the patch!  It was
already discussed and commented in detail in the v4 of this series, [*]
so please feel free to include:

Reviewed-by: Dragan Simic <dsimic@manjaro.org>

[*] 
https://lore.kernel.org/linux-rockchip/a3b98e3d3a2571ee75e59418bb3b6960@manjaro.org/T/#u

Re: [PATCH v5 1/4] arm64: dts: rockchip: add overlay test for WolfVision PF5

[Quentin Schulz]

Hi Dragan,

On 2/10/25 9:46 AM, Dragan Simic wrote:
> Hello Quentin,
> 
> Please see a few comments below.
> 
> On 2025-02-07 16:19, Quentin Schulz wrote:
>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>
>> The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO Expander
>> board connected to it. Therefore, let's generate an overlay test so the
>> application of the two overlays are validated against the base DTB.
>>
>> Suggested-by: Michael Riesch <michael.riesch@wolfvision.net>
>> Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>>
>> ---
>>  arch/arm64/boot/dts/rockchip/Makefile | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
>> b/arch/arm64/boot/dts/rockchip/Makefile
>> index
>> def1222c1907eb16b23cff6d540174a4e897abc9..534e70a649eeada7f9b6f12596b83f5c47b184b4
>> 100644
>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>> @@ -170,3 +170,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s- 
>> orangepi-5.dtb
>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
>> +
>> +# Overlay application tests
>> +#
>> +# A .dtbo must have its own
>> +#
>> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo
>> +#
>> +# entry, and at least one overlay application test - ideally 
>> reflecting how it
>> +# will be used in real life -:
> 
> Hmm, what's "-:" actually doing in the line right above?  I mean,
> it's a minor nitpick, so might be worth addressing only if there
> will be the v6...  Also, "test - ideally" might be replaced by
> "test, ideally", because splicing sentences together using em/en
> dashes is generally frowned upon. :)
> 

That was supposed to be an em-dash yes.

, and at least one overlay application test (ideally reflecting how it 
will be used in real life):

Would that work? I don't like the : following "ideally reflecting how it 
will be used in real life" as it applies to "overlay application test" 
and not the end of the sentence.

>> +#
>> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <name of overlay application test>.dtb
>> +#  <name of overlay application test>-dtbs := <base>.dtb
>> <overlay-1>.dtbo [<overlay-2>.dtbo ...]
> 
> As another minor nitpick, I'd suggest that
> 
>      "<name of overlay application test>.dtb"
> 
> is replaced with
> 
>      "<name-of-overlay-application-test>.dtb"
> 

OK.

Cheers,
Quentin

Re: [PATCH v5 1/4] arm64: dts: rockchip: add overlay test for WolfVision PF5

[Dragan Simic]

Hello Quentin,

On 2025-02-10 18:56, Quentin Schulz wrote:
> On 2/10/25 9:46 AM, Dragan Simic wrote:
>> On 2025-02-07 16:19, Quentin Schulz wrote:
>>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>> 
>>> The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO 
>>> Expander
>>> board connected to it. Therefore, let's generate an overlay test so 
>>> the
>>> application of the two overlays are validated against the base DTB.
>>> 
>>> Suggested-by: Michael Riesch <michael.riesch@wolfvision.net>
>>> Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
>>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>>> 
>>> ---
>>>  arch/arm64/boot/dts/rockchip/Makefile | 22 ++++++++++++++++++++++
>>>  1 file changed, 22 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
>>> b/arch/arm64/boot/dts/rockchip/Makefile
>>> index
>>> def1222c1907eb16b23cff6d540174a4e897abc9..534e70a649eeada7f9b6f12596b83f5c47b184b4
>>> 100644
>>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>>> @@ -170,3 +170,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s- 
>>> orangepi-5.dtb
>>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
>>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
>>>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
>>> +
>>> +# Overlay application tests
>>> +#
>>> +# A .dtbo must have its own
>>> +#
>>> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo
>>> +#
>>> +# entry, and at least one overlay application test - ideally 
>>> reflecting how it
>>> +# will be used in real life -:
>> 
>> Hmm, what's "-:" actually doing in the line right above?  I mean,
>> it's a minor nitpick, so might be worth addressing only if there
>> will be the v6...  Also, "test - ideally" might be replaced by
>> "test, ideally", because splicing sentences together using em/en
>> dashes is generally frowned upon. :)
> 
> That was supposed to be an em-dash yes.

I see.  To explain it a bit further, here's how hyphens, en and em
dashes should look like when an unproportional font is used:

- When it comes to hyphens, it's a somewhat-limited option.
- Using en dashes -- as visible here -- is a bit more involved.
- If you use em dashes---like here---it gets borderline ugly.

> , and at least one overlay application test (ideally reflecting how it
> will be used in real life):
> 
> Would that work? I don't like the : following "ideally reflecting how
> it will be used in real life" as it applies to "overlay application
> test" and not the end of the sentence.

It works, although I'd suggest that a comma is added after "ideally".
Technically, it would be better not to use parentheses here, but it's
still fine.  Though, here's another option for the wording:

   , and at least one overlay application test that represents
   the overlay's intended real-life use:

>>> +#
>>> +#  dtb-$(CONFIG_ARCH_ROCKCHIP) += <name of overlay application 
>>> test>.dtb
>>> +#  <name of overlay application test>-dtbs := <base>.dtb
>>> <overlay-1>.dtbo [<overlay-2>.dtbo ...]
>> 
>> As another minor nitpick, I'd suggest that
>> 
>>      "<name of overlay application test>.dtb"
>> 
>> is replaced with
>> 
>>      "<name-of-overlay-application-test>.dtb"
> 
> OK.

Thanks.

[PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

The Edgeble NCM6A can have WiFi modules connected and this is handled
via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
NCM6A WiFi6 Overlay")).

In order to make sure the overlay is still valid in the future, let's
add a validation test by applying the overlay on top of the main base
at build time.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
 rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
 	rk3568-wolfvision-pf5-display-vz.dtbo \
 	rk3568-wolfvision-pf5-io-expander.dtbo
+
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
+rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
+	rk3588-edgeble-neu6a-wifi.dtbo

-- 
2.48.1

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Dragan Simic]

On 2025-02-07 16:19, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> The Edgeble NCM6A can have WiFi modules connected and this is handled
> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
> NCM6A WiFi6 Overlay")).
> 
> In order to make sure the overlay is still valid in the future, let's
> add a validation test by applying the overlay on top of the main base
> at build time.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
> b/arch/arm64/boot/dts/rockchip/Makefile
> index
> 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e
> 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=
> rk3568-wolfvision-pf5-vz-2-uhd.dtb
>  rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
>  	rk3568-wolfvision-pf5-display-vz.dtbo \
>  	rk3568-wolfvision-pf5-io-expander.dtbo
> +
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
> +	rk3588-edgeble-neu6a-wifi.dtbo

Looking good to me, thanks for the patch!  It was already discussed
and commented in detail in the v4 of this series, [*] so please feel
free to include:

Reviewed-by: Dragan Simic <dsimic@manjaro.org>

[*] 
https://lore.kernel.org/linux-rockchip/a3b98e3d3a2571ee75e59418bb3b6960@manjaro.org/T/#u

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Jagan Teki]

On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> wrote:
>
> From: Quentin Schulz <quentin.schulz@cherry.de>
>
> The Edgeble NCM6A can have WiFi modules connected and this is handled
> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
> NCM6A WiFi6 Overlay")).
>
> In order to make sure the overlay is still valid in the future, let's
> add a validation test by applying the overlay on top of the main base
> at build time.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
>  rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
>         rk3568-wolfvision-pf5-display-vz.dtbo \
>         rk3568-wolfvision-pf5-io-expander.dtbo
> +
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
> +       rk3588-edgeble-neu6a-wifi.dtbo

Please add neu6b-io as well, wifi dtbo is similar for it as well.

Thanks,
Jagan.

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Quentin Schulz]

Hi Jagan,

On 2/10/25 3:11 PM, Jagan Teki wrote:
> On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> wrote:
>>
>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>
>> The Edgeble NCM6A can have WiFi modules connected and this is handled
>> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
>> NCM6A WiFi6 Overlay")).
>>
>> In order to make sure the overlay is still valid in the future, let's
>> add a validation test by applying the overlay on top of the main base
>> at build time.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>> ---
>>   arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
>> index 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 100644
>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
>>   rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
>>          rk3568-wolfvision-pf5-display-vz.dtbo \
>>          rk3568-wolfvision-pf5-io-expander.dtbo
>> +
>> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
>> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>> +       rk3588-edgeble-neu6a-wifi.dtbo
> 
> Please add neu6b-io as well, wifi dtbo is similar for it as well.
> 

Similar or identical :)?

Should the overlay be renamed if it applies to neu6b AND neu6a instead 
of implying it's only for neu6a based on the name of the overlay?

Cheers,
Quentin

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Dragan Simic]

Hello Quentin and Jagan,

On 2025-02-10 18:57, Quentin Schulz wrote:
> On 2/10/25 3:11 PM, Jagan Teki wrote:
>> On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> 
>> wrote:
>>> 
>>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>> 
>>> The Edgeble NCM6A can have WiFi modules connected and this is handled
>>> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add 
>>> Edgeble
>>> NCM6A WiFi6 Overlay")).
>>> 
>>> In order to make sure the overlay is still valid in the future, let's
>>> add a validation test by applying the overlay on top of the main base
>>> at build time.
>>> 
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>>> ---
>>>   arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>>>   1 file changed, 4 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile 
>>> b/arch/arm64/boot/dts/rockchip/Makefile
>>> index 
>>> 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 
>>> 100644
>>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>>> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += 
>>> rk3568-wolfvision-pf5-vz-2-uhd.dtb
>>>   rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
>>>          rk3568-wolfvision-pf5-display-vz.dtbo \
>>>          rk3568-wolfvision-pf5-io-expander.dtbo
>>> +
>>> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
>>> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>>> +       rk3588-edgeble-neu6a-wifi.dtbo
>> 
>> Please add neu6b-io as well, wifi dtbo is similar for it as well.
> 
> Similar or identical :)?
> 
> Should the overlay be renamed if it applies to neu6b AND neu6a instead
> of implying it's only for neu6a based on the name of the overlay?

I'm afraid it's a bit too late for renaming the .dtso file. :/
Though, the DT overlay tests could also serve as some kind of
documentation about what overlay can get applied to what base
.dtb, making this situation a bit better.

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Quentin Schulz]

Hi Dragan,

On 2/10/25 7:29 PM, Dragan Simic wrote:
> Hello Quentin and Jagan,
> 
> On 2025-02-10 18:57, Quentin Schulz wrote:
>> On 2/10/25 3:11 PM, Jagan Teki wrote:
>>> On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> 
>>> wrote:
>>>>
>>>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>>>
>>>> The Edgeble NCM6A can have WiFi modules connected and this is handled
>>>> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
>>>> NCM6A WiFi6 Overlay")).
>>>>
>>>> In order to make sure the overlay is still valid in the future, let's
>>>> add a validation test by applying the overlay on top of the main base
>>>> at build time.
>>>>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>>>> ---
>>>>   arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>>>>   1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/ 
>>>> boot/dts/rockchip/Makefile
>>>> index 
>>>> 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 100644
>>>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>>>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>>>> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568- 
>>>> wolfvision-pf5-vz-2-uhd.dtb
>>>>   rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
>>>>          rk3568-wolfvision-pf5-display-vz.dtbo \
>>>>          rk3568-wolfvision-pf5-io-expander.dtbo
>>>> +
>>>> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
>>>> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>>>> +       rk3588-edgeble-neu6a-wifi.dtbo
>>>
>>> Please add neu6b-io as well, wifi dtbo is similar for it as well.
>>
>> Similar or identical :)?
>>
>> Should the overlay be renamed if it applies to neu6b AND neu6a instead
>> of implying it's only for neu6a based on the name of the overlay?
> 
> I'm afraid it's a bit too late for renaming the .dtso file. :/

How is it too late? Is there some rule somewhere about renaming I missed?

Cheers,
Quentin

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Dragan Simic]

Hello Quentin,

On 2025-02-11 13:59, Quentin Schulz wrote:
> On 2/10/25 7:29 PM, Dragan Simic wrote:
>> On 2025-02-10 18:57, Quentin Schulz wrote:
>>> On 2/10/25 3:11 PM, Jagan Teki wrote:
>>>> On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> 
>>>> wrote:
>>>>> 
>>>>> From: Quentin Schulz <quentin.schulz@cherry.de>
>>>>> 
>>>>> The Edgeble NCM6A can have WiFi modules connected and this is 
>>>>> handled
>>>>> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add 
>>>>> Edgeble
>>>>> NCM6A WiFi6 Overlay")).
>>>>> 
>>>>> In order to make sure the overlay is still valid in the future, 
>>>>> let's
>>>>> add a validation test by applying the overlay on top of the main 
>>>>> base
>>>>> at build time.
>>>>> 
>>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
>>>>> ---
>>>>>   arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
>>>>>   1 file changed, 4 insertions(+)
>>>>> 
>>>>> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/ 
>>>>> boot/dts/rockchip/Makefile
>>>>> index 
>>>>> 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 
>>>>> 100644
>>>>> --- a/arch/arm64/boot/dts/rockchip/Makefile
>>>>> +++ b/arch/arm64/boot/dts/rockchip/Makefile
>>>>> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568- 
>>>>> wolfvision-pf5-vz-2-uhd.dtb
>>>>>   rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb 
>>>>> \
>>>>>          rk3568-wolfvision-pf5-display-vz.dtbo \
>>>>>          rk3568-wolfvision-pf5-io-expander.dtbo
>>>>> +
>>>>> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
>>>>> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>>>>> +       rk3588-edgeble-neu6a-wifi.dtbo
>>>> 
>>>> Please add neu6b-io as well, wifi dtbo is similar for it as well.
>>> 
>>> Similar or identical :)?
>>> 
>>> Should the overlay be renamed if it applies to neu6b AND neu6a 
>>> instead
>>> of implying it's only for neu6a based on the name of the overlay?
>> 
>> I'm afraid it's a bit too late for renaming the .dtso file. :/
> 
> How is it too late? Is there some rule somewhere about renaming I 
> missed?

The way I see it, names of the .dts and .dtso files become part of
the "extended ABI", so to speak, once they've been accepted upstream
for a while, because renaming them may break boot configurations.

Re: [PATCH v5 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A

[Jagan Teki]

Hi Quentin,

On Mon, 10 Feb 2025 at 23:27, Quentin Schulz <quentin.schulz@cherry.de> wrote:
>
> Hi Jagan,
>
> On 2/10/25 3:11 PM, Jagan Teki wrote:
> > On Fri, 7 Feb 2025 at 20:50, Quentin Schulz <foss+kernel@0leil.net> wrote:
> >>
> >> From: Quentin Schulz <quentin.schulz@cherry.de>
> >>
> >> The Edgeble NCM6A can have WiFi modules connected and this is handled
> >> via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble
> >> NCM6A WiFi6 Overlay")).
> >>
> >> In order to make sure the overlay is still valid in the future, let's
> >> add a validation test by applying the overlay on top of the main base
> >> at build time.
> >>
> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> >> ---
> >>   arch/arm64/boot/dts/rockchip/Makefile | 4 ++++
> >>   1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> >> index 534e70a649eeada7f9b6f12596b83f5c47b184b4..02f98abe1df10f44f2ac27ea5f6c6e6c6334724e 100644
> >> --- a/arch/arm64/boot/dts/rockchip/Makefile
> >> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> >> @@ -192,3 +192,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
> >>   rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
> >>          rk3568-wolfvision-pf5-display-vz.dtbo \
> >>          rk3568-wolfvision-pf5-io-expander.dtbo
> >> +
> >> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
> >> +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
> >> +       rk3588-edgeble-neu6a-wifi.dtbo
> >
> > Please add neu6b-io as well, wifi dtbo is similar for it as well.
> >
>
> Similar or identical :)?
>
> Should the overlay be renamed if it applies to neu6b AND neu6a instead
> of implying it's only for neu6a based on the name of the overlay?

Similar. that overlay is applicable for neu6a-io and neu6b-io both.

Thanks,
Jagan.

[PATCH v5 3/4] arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlays

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

According to commit 40658534756f ("arm64: dts: rockchip: Add rock5b
overlays for PCIe endpoint mode"), Rock 5B can operate in PCIe endpoint
mode. For that to work, the rk3588-rock-5b-pcie-ep.dtbo overlay needs to
be applied on Rock 5B base Device Tree. If that Rock 5B is connected to
another Rock 5B, the latter needs to apply the
rk3588-rock-5b-pcie-srns.dtbo overlay.

In order to make sure the overlays are still valid in the future, let's
add a validation test by applying the overlays on top of the main base
at build time.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 arch/arm64/boot/dts/rockchip/Makefile | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 02f98abe1df10f44f2ac27ea5f6c6e6c6334724e..8f93e0c4d6032d0ca2d93f44384c027e53aa5efb 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -196,3 +196,11 @@ rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
 rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
 	rk3588-edgeble-neu6a-wifi.dtbo
+
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb
+rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \
+	rk3588-rock-5b-pcie-ep.dtbo
+
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb
+rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \
+	rk3588-rock-5b-pcie-srns.dtbo

-- 
2.48.1

Re: [PATCH v5 3/4] arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlays

[Dragan Simic]

On 2025-02-07 16:20, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> According to commit 40658534756f ("arm64: dts: rockchip: Add rock5b
> overlays for PCIe endpoint mode"), Rock 5B can operate in PCIe endpoint
> mode. For that to work, the rk3588-rock-5b-pcie-ep.dtbo overlay needs 
> to
> be applied on Rock 5B base Device Tree. If that Rock 5B is connected to
> another Rock 5B, the latter needs to apply the
> rk3588-rock-5b-pcie-srns.dtbo overlay.
> 
> In order to make sure the overlays are still valid in the future, let's
> add a validation test by applying the overlays on top of the main base
> at build time.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
> b/arch/arm64/boot/dts/rockchip/Makefile
> index
> 02f98abe1df10f44f2ac27ea5f6c6e6c6334724e..8f93e0c4d6032d0ca2d93f44384c027e53aa5efb
> 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -196,3 +196,11 @@ rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=
> rk3568-wolfvision-pf5.dtb \
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
>  rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>  	rk3588-edgeble-neu6a-wifi.dtbo
> +
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb
> +rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \
> +	rk3588-rock-5b-pcie-ep.dtbo
> +
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb
> +rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \
> +	rk3588-rock-5b-pcie-srns.dtbo

Looking good to me, thanks for the patch!  The employed approach was
already discussed and commented in detail in the v4 of this series, [*]
so please feel free to include:

Reviewed-by: Dragan Simic <dsimic@manjaro.org>

[*] 
https://lore.kernel.org/linux-rockchip/a3b98e3d3a2571ee75e59418bb3b6960@manjaro.org/T/#u

[PATCH v5 4/4] arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

The Pre-ICT tester adapter connects to RK3588 Jaguar SBC through its
proprietary Mezzanine connector.

It exposes a PCIe Gen2 1x M.2 connector and two proprietary camera
connectors. Support for the latter will come once the rest of the camera
stack is supported.

Additionally, the adapter loops some GPIOs together as well as route
some GPIOs to power rails.

This adapter is used for manufacturing RK3588 Jaguar to be able to test
the Mezzanine connector is properly soldered.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 arch/arm64/boot/dts/rockchip/Makefile              |   5 +
 .../dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso | 171 +++++++++++++++++++++
 2 files changed, 176 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 8f93e0c4d6032d0ca2d93f44384c027e53aa5efb..58664453e019496420dfec7b781cc313fab04185 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
@@ -197,6 +198,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
 rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
 	rk3588-edgeble-neu6a-wifi.dtbo
 
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtb
+rk3588-jaguar-pre-ict-tester-dtbs := rk3588-jaguar.dtb \
+	rk3588-jaguar-pre-ict-tester.dtbo
+
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb
 rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \
 	rk3588-rock-5b-pcie-ep.dtbo
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..9d44dfe2f30d793accb994a230c58038f0c3daad
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2024 Cherry Embedded Solutions GmbH
+ *
+ * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine
+ * connector on RK3588 Jaguar.
+ *
+ * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary
+ * camera connectors (each their own I2C bus, clock, reset and PWM lines as well
+ * as 2-lane CSI).
+ *
+ * This adapter routes some GPIOs to power rails and loops together some other
+ * GPIOs.
+ *
+ * This adapter is used during manufacturing for validating proper soldering of
+ * the mezzanine connector.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+	pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "pre_ict_tester_vcc_1v2";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pre_ict_tester_vcc_2v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&gpio3 {
+	pinctrl-0 = <&pre_ict_pwr2gpio>;
+	pinctrl-names = "default";
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2x1l2_perstn_m0>;
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+};
+
+&pinctrl {
+	pcie2x1l2 {
+		pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pre-ict-tester {
+		pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins {
+			rockchip,pins =
+			/*
+			 * GPIO3_A3 requires two power rails to be properly
+			 * routed to the mezzanine connector to report a proper
+			 * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an
+			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
+			 * but GPIO3_C6 would catch this HW soldering issue.
+			 * If VCC_IN_2 is properly routed, GPIO3_A3 should be
+			 * LOW. The signal shall not read HIGH in the event
+			 * GPIO3_A3 isn't properly routed due to soldering
+			 * issue. Therefore, let's enforce a pull-up (which is
+			 * the SoC default for this pin).
+			 */
+				<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+			/*
+			 * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power
+			 * rail. It should be HIGH if all is properly soldered.
+			 * To guarantee that, a pull-down is enforced (which is
+			 * the SoC default for this pin) so that LOW is read if
+			 * the loop doesn't exist on HW (soldering issue on
+			 * either signals).
+			 */
+				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
+			/*
+			 * GPIO3_B2 requires two power rails to be properly
+			 * routed to the mezzanine connector to report a proper
+			 * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an
+			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
+			 * but GPIO3_C6 would catch this HW soldering issue.
+			 * If VCC_IN_1 is properly routed, GPIO3_B2 should be
+			 * LOW. This is an issue if GPIO3_B2 isn't properly
+			 * routed due to soldering issue, because GPIO3_B2
+			 * default bias is pull-down therefore being LOW. So
+			 * the worst case scenario and the pass scenario expect
+			 * the same value. Make GPIO3_B2 a pull-up so that a
+			 * soldering issue on GPIO3_B2 reports HIGH but proper
+			 * soldering reports LOW.
+			 */
+				<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+			/*
+			 * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power
+			 * rail. It should be HIGH if all is properly soldered.
+			 * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't
+			 * properly routed due to soldering issue, because
+			 * GPIO3_C6 default bias is pull-up therefore being HIGH
+			 * in all cases:
+			 *  - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not
+			 *    routed properly,
+			 *  - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is
+			 *    not routed properly,
+			 *  - GPIO3_C6 is HIGH if everything is proper,
+			 * Make GPIO3_C6 a pull-down so that a soldering issue
+			 * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper
+			 * soldering reports HIGH.
+			 */
+				<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>,
+			/*
+			 * GPIO3_D2 is routed to VCC_5V0_1 power rail through a
+			 * voltage divider on the adapter.
+			 * It should be HIGH if all is properly soldered.
+			 * To guarantee that, a pull-down is enforced (which is
+			 * the SoC default for this pin) so that LOW is read if
+			 * the loop doesn't exist on HW (soldering issue on
+			 * either signals).
+			 */
+				<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>,
+			/*
+			 * GPIO3_D3 is routed to VCC_5V0_2 power rail through a
+			 * voltage divider on the adapter.
+			 * It should be HIGH if all is properly soldered.
+			 * To guarantee that, a pull-down is enforced (which is
+			 * the SoC default for this pin) so that LOW is read if
+			 * the loop doesn't exist on HW (soldering issue on
+			 * either signals).
+			 */
+				<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>,
+			/*
+			 * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through
+			 * a voltage divider on the adapter.
+			 * It should be HIGH if all is properly soldered.
+			 * To guarantee that, a pull-down is enforced (which is
+			 * the SoC default for this pin) so that LOW is read if
+			 * the loop doesn't exist on HW (soldering issue on
+			 * either signals).
+			 */
+				<3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>,
+			/*
+			 * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through
+			 * a voltage divider on the adapter.
+			 * It should be HIGH if all is properly soldered.
+			 * To guarantee that, a pull-down is enforced (which is
+			 * the SoC default for this pin) so that LOW is read if
+			 * the loop doesn't exist on HW (soldering issue on
+			 * either signals).
+			 */
+				<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};

-- 
2.48.1

Re: [PATCH v5 4/4] arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar

[Dragan Simic]

On 2025-02-07 16:20, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> The Pre-ICT tester adapter connects to RK3588 Jaguar SBC through its
> proprietary Mezzanine connector.
> 
> It exposes a PCIe Gen2 1x M.2 connector and two proprietary camera
> connectors. Support for the latter will come once the rest of the 
> camera
> stack is supported.
> 
> Additionally, the adapter loops some GPIOs together as well as route
> some GPIOs to power rails.
> 
> This adapter is used for manufacturing RK3588 Jaguar to be able to test
> the Mezzanine connector is properly soldered.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile              |   5 +
>  .../dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso | 171 
> +++++++++++++++++++++
>  2 files changed, 176 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile
> b/arch/arm64/boot/dts/rockchip/Makefile
> index
> 8f93e0c4d6032d0ca2d93f44384c027e53aa5efb..58664453e019496420dfec7b781cc313fab04185
> 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += 
> rk3588-firefly-itx-3588j.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
> @@ -197,6 +198,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=
> rk3588-edgeble-neu6a-wifi.dtb
>  rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
>  	rk3588-edgeble-neu6a-wifi.dtbo
> 
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtb
> +rk3588-jaguar-pre-ict-tester-dtbs := rk3588-jaguar.dtb \
> +	rk3588-jaguar-pre-ict-tester.dtbo
> +
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb
>  rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \
>  	rk3588-rock-5b-pcie-ep.dtbo

Looking good to me, thanks for the patch!  The employed approach
was already discussed and commented in detail in the v4 of this
series, [*] so please feel free to include:

Reviewed-by: Dragan Simic <dsimic@manjaro.org>

Please note that my tag applies to the changes introduced to the
Makefile only, because I have no clue about the actual hardware
design and don't have access to the schematic of the ICT tester
described in the new .dtso file below.

[*] 
https://lore.kernel.org/linux-rockchip/a3b98e3d3a2571ee75e59418bb3b6960@manjaro.org/T/#u


> diff --git
> a/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso
> b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..9d44dfe2f30d793accb994a230c58038f0c3daad
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso
> @@ -0,0 +1,171 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (c) 2024 Cherry Embedded Solutions GmbH
> + *
> + * Device Tree Overlay for the Pre-ICT tester adapter for the 
> Mezzanine
> + * connector on RK3588 Jaguar.
> + *
> + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two 
> proprietary
> + * camera connectors (each their own I2C bus, clock, reset and PWM
> lines as well
> + * as 2-lane CSI).
> + *
> + * This adapter routes some GPIOs to power rails and loops together 
> some other
> + * GPIOs.
> + *
> + * This adapter is used during manufacturing for validating proper 
> soldering of
> + * the mezzanine connector.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +
> +&{/} {
> +	pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "pre_ict_tester_vcc_1v2";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <1200000>;
> +		regulator-max-microvolt = <1200000>;
> +		vin-supply = <&vcc_3v3_s3>;
> +	};
> +
> +	pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "pre_ict_tester_vcc_2v8";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <2800000>;
> +		regulator-max-microvolt = <2800000>;
> +		vin-supply = <&vcc_3v3_s3>;
> +	};
> +};
> +
> +&combphy0_ps {
> +	status = "okay";
> +};
> +
> +&gpio3 {
> +	pinctrl-0 = <&pre_ict_pwr2gpio>;
> +	pinctrl-names = "default";
> +};
> +
> +&pcie2x1l2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2x1l2_perstn_m0>;
> +	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* 
> PCIE20X1_2_PERSTN_M0 */
> +	vpcie3v3-supply = <&vcc_3v3_s3>;
> +	status = "okay";
> +};
> +
> +&pinctrl {
> +	pcie2x1l2 {
> +		pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 {
> +			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
> +
> +	pre-ict-tester {
> +		pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins {
> +			rockchip,pins =
> +			/*
> +			 * GPIO3_A3 requires two power rails to be properly
> +			 * routed to the mezzanine connector to report a proper
> +			 * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an
> +			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
> +			 * but GPIO3_C6 would catch this HW soldering issue.
> +			 * If VCC_IN_2 is properly routed, GPIO3_A3 should be
> +			 * LOW. The signal shall not read HIGH in the event
> +			 * GPIO3_A3 isn't properly routed due to soldering
> +			 * issue. Therefore, let's enforce a pull-up (which is
> +			 * the SoC default for this pin).
> +			 */
> +				<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
> +			/*
> +			 * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power
> +			 * rail. It should be HIGH if all is properly soldered.
> +			 * To guarantee that, a pull-down is enforced (which is
> +			 * the SoC default for this pin) so that LOW is read if
> +			 * the loop doesn't exist on HW (soldering issue on
> +			 * either signals).
> +			 */
> +				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
> +			/*
> +			 * GPIO3_B2 requires two power rails to be properly
> +			 * routed to the mezzanine connector to report a proper
> +			 * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an
> +			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
> +			 * but GPIO3_C6 would catch this HW soldering issue.
> +			 * If VCC_IN_1 is properly routed, GPIO3_B2 should be
> +			 * LOW. This is an issue if GPIO3_B2 isn't properly
> +			 * routed due to soldering issue, because GPIO3_B2
> +			 * default bias is pull-down therefore being LOW. So
> +			 * the worst case scenario and the pass scenario expect
> +			 * the same value. Make GPIO3_B2 a pull-up so that a
> +			 * soldering issue on GPIO3_B2 reports HIGH but proper
> +			 * soldering reports LOW.
> +			 */
> +				<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
> +			/*
> +			 * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power
> +			 * rail. It should be HIGH if all is properly soldered.
> +			 * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't
> +			 * properly routed due to soldering issue, because
> +			 * GPIO3_C6 default bias is pull-up therefore being HIGH
> +			 * in all cases:
> +			 *  - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not
> +			 *    routed properly,
> +			 *  - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is
> +			 *    not routed properly,
> +			 *  - GPIO3_C6 is HIGH if everything is proper,
> +			 * Make GPIO3_C6 a pull-down so that a soldering issue
> +			 * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper
> +			 * soldering reports HIGH.
> +			 */
> +				<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>,
> +			/*
> +			 * GPIO3_D2 is routed to VCC_5V0_1 power rail through a
> +			 * voltage divider on the adapter.
> +			 * It should be HIGH if all is properly soldered.
> +			 * To guarantee that, a pull-down is enforced (which is
> +			 * the SoC default for this pin) so that LOW is read if
> +			 * the loop doesn't exist on HW (soldering issue on
> +			 * either signals).
> +			 */
> +				<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>,
> +			/*
> +			 * GPIO3_D3 is routed to VCC_5V0_2 power rail through a
> +			 * voltage divider on the adapter.
> +			 * It should be HIGH if all is properly soldered.
> +			 * To guarantee that, a pull-down is enforced (which is
> +			 * the SoC default for this pin) so that LOW is read if
> +			 * the loop doesn't exist on HW (soldering issue on
> +			 * either signals).
> +			 */
> +				<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>,
> +			/*
> +			 * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through
> +			 * a voltage divider on the adapter.
> +			 * It should be HIGH if all is properly soldered.
> +			 * To guarantee that, a pull-down is enforced (which is
> +			 * the SoC default for this pin) so that LOW is read if
> +			 * the loop doesn't exist on HW (soldering issue on
> +			 * either signals).
> +			 */
> +				<3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>,
> +			/*
> +			 * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through
> +			 * a voltage divider on the adapter.
> +			 * It should be HIGH if all is properly soldered.
> +			 * To guarantee that, a pull-down is enforced (which is
> +			 * the SoC default for this pin) so that LOW is read if
> +			 * the loop doesn't exist on HW (soldering issue on
> +			 * either signals).
> +			 */
> +				<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
> +		};
> +	};
> +};