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Tue, 30 Jan 2024 08:27:09 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40U8R8Sl025543 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 Jan 2024 08:27:08 GMT Received: from [10.206.101.41] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 30 Jan 2024 00:27:03 -0800 Message-ID: Date: Tue, 30 Jan 2024 13:56:59 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] media: dt-bindings: qcom,sc7280-venus: Allow one IOMMU entry Content-Language: en-US To: Luca Weiss , Conor Dooley CC: Bjorn Andersson , Konrad Dybcio , Stanimir Varbanov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , <~postmarketos/upstreaming@lists.sr.ht>, , Stanimir Varbanov , , , , References: <20240129-sc7280-venus-bindings-v1-1-20a9ba194c60@fairphone.com> <20240129-numerate-brought-4660c2a89719@spud> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Xv8y1pP61jrbaPJVNBCBn_IPG2vNeojm X-Proofpoint-ORIG-GUID: Xv8y1pP61jrbaPJVNBCBn_IPG2vNeojm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-30_02,2024-01-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=805 spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 clxscore=1011 adultscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401300060 Hello, On 1/30/2024 1:17 PM, Luca Weiss wrote: > On Mon Jan 29, 2024 at 6:37 PM CET, Conor Dooley wrote: >> On Mon, Jan 29, 2024 at 08:48:54AM +0100, Luca Weiss wrote: >>> Some SC7280-based boards crash when providing the "secure_non_pixel" >>> context bank, so allow only one iommu in the bindings also. >>> >>> Signed-off-by: Luca Weiss >> >> Do we have any idea why this happens? How is someone supposed to know >> whether or not their system requires you to only provide one iommu? >> Yes, a crash might be the obvious answer, but is there a way of knowing >> without the crashes? > > +CC Vikash Garodia > > Unfortunately I don't really have much more information than this > message here: > https://lore.kernel.org/linux-arm-msm/ff021f49-f81b-0fd1-bd2c-895dbbb03d56@quicinc.com/ > > And see also the following replies for a bit more context, like this > one: > https://lore.kernel.org/linux-arm-msm/a4e8b531-49f9-f4a1-51cb-e422c56281cc@quicinc.com/ > > Maybe Vikash can add some more info regarding this. 0x2184 is a secure SID i.e any transactions with that ID would be access controlled by trustzone (TZ). SC7280 (chromebook) was designed without TZ, while some other DT deriving from SC7280 (like qcm6490) might have TZ. Hence it is good to move the iommu entry from SC7280 to chrome-common. Regards, Vikash