* [PATCH v2 0/3] arm64: dts: qcom: sm8650: Add CAMSS device tree node
@ 2025-04-23 22:19 Vladimir Zapolskiy
2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Vladimir Zapolskiy @ 2025-04-23 22:19 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm,
devicetree
The Qualcomm SM8650 SoC contains a camera subsystem IP, which is
got supported in the platform device tree by this change series.
Qualcomm SM8650 CAMSS IP contains of
* 6 x CSIPHY,
* 3 x CSID,
* 2 x CSID Lite,
* 3 x IFE,
* 2 x IFE Lite.
v1 version of the changeset:
- https://lore.kernel.org/linux-media/20250312001132.1832655-1-vladimir.zapolskiy@linaro.org
Changes from v1 to v2:
* to support a regex in port property names replaced 'properties' with
'patternProperties', a sanity check shall pass now, thanks to Dmitry,
* added a few new line separators between property groups in sm8650.dtsi
and qcom,sm8650-camss.yaml dt bindings documentation, thanks to Bryan,
* added the fourth interrupt cell value needed for v6.15, thanks to Neil,
* added a given Reviewed-by tag to one of the patches, thanks to Bryan,
* rebased for v6.16.
Vladimir Zapolskiy (3):
dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
arm64: dts: qcom: sm8650: Add CAMSS block definition
arm64: dts: qcom: sm8650: Add description of MCLK pins
.../bindings/media/qcom,sm8650-camss.yaml | 394 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8650.dtsi | 333 +++++++++++++++
2 files changed, 727 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
--
2.45.2
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP 2025-04-23 22:19 [PATCH v2 0/3] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy @ 2025-04-23 22:19 ` Vladimir Zapolskiy 2025-04-23 22:26 ` Bryan O'Donoghue 2025-06-13 8:29 ` Bryan O'Donoghue 2025-04-23 22:19 ` [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition Vladimir Zapolskiy 2025-04-23 22:19 ` [PATCH v2 3/3] arm64: dts: qcom: sm8650: Add description of MCLK pins Vladimir Zapolskiy 2 siblings, 2 replies; 7+ messages in thread From: Vladimir Zapolskiy @ 2025-04-23 22:19 UTC (permalink / raw) To: Robert Foss, Todor Tomov, Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree Add device tree bindings for Qualcomm SM8650 camera subsystem. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- .../bindings/media/qcom,sm8650-camss.yaml | 394 ++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml new file mode 100644 index 000000000000..2a7c243993c4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml @@ -0,0 +1,394 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 Camera Subsystem (CAMSS) + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8650-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 36 + + clock-names: + items: + - const: camnoc_axi_nrt + - const: camnoc_axi_rt + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: cpas_vfe_lite + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy_rx + - const: gcc_ahb_clk + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: qdss_debug_xo + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 16 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + iommus: + maxItems: 3 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + vdda-csi01-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. + + vdda-csi24-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. + + vdda-csi35-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. + + vdda-csi01-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. + + vdda-csi24-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. + + vdda-csi35-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8650-camcc.h> + #include <dt-bindings/clock/qcom,sm8650-gcc.h> + #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb8000 { + compatible = "qcom,sm8650-camss"; + reg = <0 0x0acb8000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbc000 0 0x1000>, + <0 0x0accb000 0 0x1000>, + <0 0x0acd0000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accc000 0 0x2000>, + <0 0x0acd1000 0 0x2000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi_nrt", + "camnoc_axi_rt", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy_rx", + "gcc_ahb_clk", + "gcc_axi_hf", + "gcc_axi_sf", + "qdss_debug_xo", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", + "hf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>, + <&apps_smmu 0x18a0 0x40>, + <&apps_smmu 0x1860 0x00>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", "ife1", "ife2", "top"; + + vdda-csi01-0p9-supply = <&vreg_0p9>; + vdda-csi01-1p2-supply = <&vreg_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <4>; + data-lanes = <0 1>; + remote-endpoint = <&camera_sensor>; + }; + }; + }; + }; + }; -- 2.45.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP 2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy @ 2025-04-23 22:26 ` Bryan O'Donoghue 2025-06-13 8:29 ` Bryan O'Donoghue 1 sibling, 0 replies; 7+ messages in thread From: Bryan O'Donoghue @ 2025-04-23 22:26 UTC (permalink / raw) To: Vladimir Zapolskiy, Robert Foss, Todor Tomov, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree On 23/04/2025 23:19, Vladimir Zapolskiy wrote: > Add device tree bindings for Qualcomm SM8650 camera subsystem. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > .../bindings/media/qcom,sm8650-camss.yaml | 394 ++++++++++++++++++ > 1 file changed, 394 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > new file mode 100644 > index 000000000000..2a7c243993c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > @@ -0,0 +1,394 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8650 Camera Subsystem (CAMSS) > + > +maintainers: > + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8650-camss > + > + reg: > + maxItems: 17 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_wrapper > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + clocks: > + maxItems: 36 > + > + clock-names: > + items: > + - const: camnoc_axi_nrt > + - const: camnoc_axi_rt > + - const: cpas_ahb > + - const: cpas_fast_ahb > + - const: cpas_vfe0 > + - const: cpas_vfe1 > + - const: cpas_vfe2 > + - const: cpas_vfe_lite > + - const: csid > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy5 > + - const: csiphy5_timer > + - const: csiphy_rx > + - const: gcc_ahb_clk > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: qdss_debug_xo > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe1 > + - const: vfe1_fast_ahb > + - const: vfe2 > + - const: vfe2_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 16 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 3 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_0_mnoc > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: ife2 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + patternProperties: > + "^port@[0-5]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data from a CSIPHY. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + vdda-csi01-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. > + > + vdda-csi01-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domain-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8650-camcc.h> > + #include <dt-bindings/clock/qcom,sm8650-gcc.h> > + #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + isp@acb8000 { > + compatible = "qcom,sm8650-camss"; > + reg = <0 0x0acb8000 0 0x1000>, > + <0 0x0acba000 0 0x1000>, > + <0 0x0acbc000 0 0x1000>, > + <0 0x0accb000 0 0x1000>, > + <0 0x0acd0000 0 0x1000>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acea000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acee000 0 0x2000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0ac80000 0 0xf000>, > + <0 0x0accc000 0 0x2000>, > + <0 0x0acd1000 0 0x2000>; > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_wrapper", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_2_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY5_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_2_CLK>, > + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + clock-names = "camnoc_axi_nrt", > + "camnoc_axi_rt", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe2", > + "cpas_vfe_lite", > + "csid", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "csiphy4", > + "csiphy4_timer", > + "csiphy5", > + "csiphy5_timer", > + "csiphy_rx", > + "gcc_ahb_clk", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "qdss_debug_xo", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe2", > + "vfe2_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "ahb", > + "hf_0_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x20>, > + <&apps_smmu 0x18a0 0x40>, > + <&apps_smmu 0x1860 0x00>; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_IFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", "ife1", "ife2", "top"; > + > + vdda-csi01-0p9-supply = <&vreg_0p9>; > + vdda-csi01-1p2-supply = <&vreg_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csiphy1_ep: endpoint { > + clock-lanes = <4>; > + data-lanes = <0 1>; > + remote-endpoint = <&camera_sensor>; > + }; > + }; > + }; > + }; > + }; Fine by me I have no real objection/concern with extending out the regulator names - as we've discussed, this is a more accurate description of the underlying hardware than we have thus far had. Please add in the csitpg to the description too though. csitpg0 csitpg1 ... csitpgX Then you can add Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> to this and the dts that accompanies. --- bod ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP 2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy 2025-04-23 22:26 ` Bryan O'Donoghue @ 2025-06-13 8:29 ` Bryan O'Donoghue 1 sibling, 0 replies; 7+ messages in thread From: Bryan O'Donoghue @ 2025-06-13 8:29 UTC (permalink / raw) To: Vladimir Zapolskiy, Robert Foss, Todor Tomov, Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree On 23/04/2025 23:19, Vladimir Zapolskiy wrote: > Add device tree bindings for Qualcomm SM8650 camera subsystem. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > .../bindings/media/qcom,sm8650-camss.yaml | 394 ++++++++++++++++++ > 1 file changed, 394 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > new file mode 100644 > index 000000000000..2a7c243993c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > @@ -0,0 +1,394 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8650 Camera Subsystem (CAMSS) > + > +maintainers: > + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8650-camss > + > + reg: > + maxItems: 17 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_wrapper > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + clocks: > + maxItems: 36 > + > + clock-names: > + items: > + - const: camnoc_axi_nrt > + - const: camnoc_axi_rt > + - const: cpas_ahb > + - const: cpas_fast_ahb > + - const: cpas_vfe0 > + - const: cpas_vfe1 > + - const: cpas_vfe2 > + - const: cpas_vfe_lite > + - const: csid > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy5 > + - const: csiphy5_timer > + - const: csiphy_rx > + - const: gcc_ahb_clk > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: qdss_debug_xo > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe1 > + - const: vfe1_fast_ahb > + - const: vfe2 > + - const: vfe2_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 16 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 3 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_0_mnoc > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: ife2 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + patternProperties: > + "^port@[0-5]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data from a CSIPHY. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + vdda-csi01-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. > + > + vdda-csi01-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. I think we should just do this + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. and loop back to add multiple rails later. Please consider doing a V3 of this along these lines so we can unblock this submission. --- bod ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition 2025-04-23 22:19 [PATCH v2 0/3] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy 2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy @ 2025-04-23 22:19 ` Vladimir Zapolskiy 2025-04-23 22:22 ` Bryan O'Donoghue 2025-04-23 22:19 ` [PATCH v2 3/3] arm64: dts: qcom: sm8650: Add description of MCLK pins Vladimir Zapolskiy 2 siblings, 1 reply; 7+ messages in thread From: Vladimir Zapolskiy @ 2025-04-23 22:19 UTC (permalink / raw) To: Robert Foss, Todor Tomov, Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree Add SM8650 CAMSS device tree node to the platform dtsi file, it contains of * 6 x CSIPHY * 3 x CSID * 2 x CSID Lite * 3 x IFE * 2 x IFE Lite Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 189 +++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c2937f721794..b24ab52413f6 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5065,6 +5065,195 @@ cci2_i2c1: i2c-bus@1 { }; }; + camss: isp@acb8000 { + compatible = "qcom,sm8650-camss"; + reg = <0 0x0acb8000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbc000 0 0x1000>, + <0 0x0accb000 0 0x1000>, + <0 0x0acd0000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accc000 0 0x2000>, + <0 0x0acd1000 0 0x2000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi_nrt", + "camnoc_axi_rt", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy_rx", + "gcc_ahb_clk", + "gcc_axi_hf", + "gcc_axi_sf", + "qdss_debug_xo", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", + "hf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>, + <&apps_smmu 0x18a0 0x40>, + <&apps_smmu 0x1860 0x00>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", "ife1", "ife2", "top"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sm8650-camcc"; reg = <0 0x0ade0000 0 0x20000>; -- 2.45.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition 2025-04-23 22:19 ` [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition Vladimir Zapolskiy @ 2025-04-23 22:22 ` Bryan O'Donoghue 0 siblings, 0 replies; 7+ messages in thread From: Bryan O'Donoghue @ 2025-04-23 22:22 UTC (permalink / raw) To: Vladimir Zapolskiy, Robert Foss, Todor Tomov, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree On 23/04/2025 23:19, Vladimir Zapolskiy wrote: > Add SM8650 CAMSS device tree node to the platform dtsi file, > it contains of > * 6 x CSIPHY > * 3 x CSID > * 2 x CSID Lite > * 3 x IFE > * 2 x IFE Lite > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 189 +++++++++++++++++++++++++++ > 1 file changed, 189 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index c2937f721794..b24ab52413f6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -5065,6 +5065,195 @@ cci2_i2c1: i2c-bus@1 { > }; > }; > > + camss: isp@acb8000 { > + compatible = "qcom,sm8650-camss"; > + reg = <0 0x0acb8000 0 0x1000>, > + <0 0x0acba000 0 0x1000>, > + <0 0x0acbc000 0 0x1000>, > + <0 0x0accb000 0 0x1000>, > + <0 0x0acd0000 0 0x1000>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acea000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acee000 0 0x2000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0ac80000 0 0xf000>, > + <0 0x0accc000 0 0x2000>, > + <0 0x0acd1000 0 0x2000>; > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_wrapper", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; Could you please include csiphytpgX for whatever number of TPGs 8650 has. Otherwise looks good. --- bod ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] arm64: dts: qcom: sm8650: Add description of MCLK pins 2025-04-23 22:19 [PATCH v2 0/3] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy 2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy 2025-04-23 22:19 ` [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition Vladimir Zapolskiy @ 2025-04-23 22:19 ` Vladimir Zapolskiy 2 siblings, 0 replies; 7+ messages in thread From: Vladimir Zapolskiy @ 2025-04-23 22:19 UTC (permalink / raw) To: Robert Foss, Todor Tomov, Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, linux-media, linux-arm-msm, devicetree Add fixed MCLK pin descriptions for all pins with such supported function. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 144 +++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index b24ab52413f6..3b13c0971d7d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5959,6 +5959,150 @@ tlmm: pinctrl@f100000 { wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam0_sleep: cam0-sleep-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam1_sleep: cam1-sleep-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam2_default: cam2-default-state { + mclk-pins { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam2_sleep: cam2-sleep-state { + mclk-pins { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam3_default: cam3-default-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam3_sleep: cam3-sleep-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam4_default: cam4-default-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam4_sleep: cam4-sleep-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam5_default: cam5-default-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam5_sleep: cam5-sleep-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam6_default: cam6-default-state { + mclk-pins { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam6_sleep: cam6-sleep-state { + mclk-pins { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam7_default: cam7-default-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam7_sleep: cam7-sleep-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio113"; -- 2.45.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-06-13 8:29 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-04-23 22:19 [PATCH v2 0/3] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy 2025-04-23 22:19 ` [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy 2025-04-23 22:26 ` Bryan O'Donoghue 2025-06-13 8:29 ` Bryan O'Donoghue 2025-04-23 22:19 ` [PATCH v2 2/3] arm64: dts: qcom: sm8650: Add CAMSS block definition Vladimir Zapolskiy 2025-04-23 22:22 ` Bryan O'Donoghue 2025-04-23 22:19 ` [PATCH v2 3/3] arm64: dts: qcom: sm8650: Add description of MCLK pins Vladimir Zapolskiy
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).