From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: wen.ping.teh@intel.com
Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org,
devicetree@vger.kernel.org, dinguyen@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, mturquette@baylibre.com,
netdev@vger.kernel.org, niravkumar.l.rabara@intel.com,
p.zabel@pengutronix.de, richardcochran@gmail.com,
robh+dt@kernel.org, sboyd@kernel.org
Subject: Re: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets
Date: Tue, 20 Jun 2023 13:06:29 +0200 [thread overview]
Message-ID: <ed6f9ab8-9c4e-ec9f-efb7-81974d75f074@linaro.org> (raw)
In-Reply-To: <20230620103930.2451721-1-wen.ping.teh@intel.com>
On 20/06/2023 12:39, wen.ping.teh@intel.com wrote:
>>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: intel,agilex5-clkmgr
>>
>>
>> Why "clkmgr", not "clk"? You did not call it Clock manager anywhere in
>> the description or title.
>>
>
> The register in Agilex5 handling the clock is named clock_mgr.
> Previous IntelSocFPGA, Agilex and Stratix10, are also named clkmgr.
So use it in description.
>
>>> +
>>> + '#clock-cells':
>>> + const: 1
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - '#clock-cells'
>>
>> Keep the same order as in properties:
>>
>
> Will update in V2 patch.
>
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + # Clock controller node:
>>> + - |
>>> + clkmgr: clock-controller@10d10000 {
>>> + compatible = "intel,agilex5-clkmgr";
>>> + reg = <0x10d10000 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +...
>>> diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h
>>> new file mode 100644
>>> index 000000000000..4505b352cd83
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/agilex5-clock.h
>>
>> Filename the same as binding. Missing vendor prefix, entirely different
>> device name.
>>
>
> Will change filename to intel,agilex5-clock.h in V2.
Read the comment - same as binding. You did not call binding that way...
unless you rename the binding.
>>
>>> +
>>> +#endif /* __AGILEX5_CLOCK_H */
>>> diff --git a/include/dt-bindings/reset/altr,rst-mgr-agilex5.h b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h
>>> new file mode 100644
>>> index 000000000000..81e5e8c89893
>>> --- /dev/null
>>> +++ b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h
>>
>> Same filename as binding.
>>
>> But why do you need this file? Your device is not a reset controller.
>
> Because Agilex5 device tree uses the reset definition from this file.
That's not the correct reason. The binding header has nothing to do with
this device. You miss another patch adding support for your device
(compatible) with this header.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-06-20 11:07 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-18 13:22 [PATCH 0/4] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-06-18 18:47 ` Krzysztof Kozlowski
2023-06-20 14:12 ` niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets niravkumar.l.rabara
2023-06-18 18:49 ` Krzysztof Kozlowski
2023-06-20 10:39 ` wen.ping.teh
2023-06-20 11:06 ` Krzysztof Kozlowski [this message]
2023-06-21 10:45 ` wen.ping.teh
2023-06-19 2:15 ` Rob Herring
2023-06-18 13:22 ` [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform niravkumar.l.rabara
2023-06-20 14:42 ` Dinh Nguyen
2023-06-18 13:22 ` [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA niravkumar.l.rabara
2023-06-18 18:56 ` Krzysztof Kozlowski
2023-06-20 14:07 ` niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-08-01 20:53 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 niravkumar.l.rabara
2023-08-01 20:55 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager niravkumar.l.rabara
2023-08-01 20:57 ` Conor Dooley
2023-08-02 3:06 ` Rabara, Niravkumar L
2023-08-02 6:58 ` Conor Dooley
2023-08-02 2:58 ` [PATCH v3 " niravkumar.l.rabara
2023-08-02 7:02 ` Conor Dooley
2023-08-02 7:14 ` Rabara, Niravkumar L
2023-08-06 17:53 ` Dinh Nguyen
2023-08-06 19:35 ` [PATCH v2 " Krzysztof Kozlowski
2023-08-07 3:56 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 niravkumar.l.rabara
2023-08-08 11:03 ` Dinh Nguyen
2023-08-09 21:28 ` Stephen Boyd
2023-08-10 10:56 ` Dinh Nguyen
2023-08-09 21:26 ` Stephen Boyd
2023-08-13 12:53 ` Rabara, Niravkumar L
2023-08-14 2:48 ` Dinh Nguyen
2023-08-14 2:59 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA niravkumar.l.rabara
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