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Thu, 15 Oct 2026 00:15:02 -0700 (PDT) X-Received: by 2002:a17:90b:1d4f:b0:3a8:c0cd:57f3 with SMTP id 98e67ed59e1d1-3ab3a94ff23mr14061583a91.18.1792048501560; Thu, 15 Oct 2026 00:15:01 -0700 (PDT) Received: from [10.217.216.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac944511c7sm3221300a91.10.2026.10.15.00.14.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 00:15:00 -0700 (PDT) Message-ID: Date: Thu, 15 Oct 2026 12:44:51 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OdENnRTY c=1 sm=1 tr=0 ts=6ad07d77 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=CaCc2b9mPIm3Huh5NNcA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: aNF-aNSHgLEJyClGUqx04_WfpTWwBksO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfXypZ5cdyFjOiY x6aiFhJWld70kItoO/2bq/lmhD2ojWFlfyT3GpPh7nw4HgQ41ew5kq/PLeUL16lQV9yI75Pxt75 vFyPYjrcFZv/Zfrb7MORbDt9slqYf1a5B6Xh8f9m2+n1iuD0zLsnqf8i9DeUvtP9emyJDOY66lf k4eydoF+brI+creYQa2+72VMELh2nOaz9PfmocRhN4Dcmhe9iUVr5+nY1tRFr/e7fT6+nrc82DQ y8/8lGnAb7bwpi/+uLjS6Qc2xSjpU68G08TyMVm0NL6oGNkwthdqjZRHEnMpiIyleBIoTmBLBLT LEk5hZHq2k6pE2ufzf2w9dlO1oyLrWlilg78JW7k2so9ur1+v4X+feS3rAvvHvHG6EkMI2zKtNG ApKRj1UrV0nr/6lyCGa8JHjG6TSyJp+zfKglYqZfI40Xwwi8GGjARdGWUJ4D39Rau0kFeHZnceL w89rjfFi115LiRxmY1w== X-Proofpoint-GUID: aNF-aNSHgLEJyClGUqx04_WfpTWwBksO X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfX59T4GlzH3W6E 53B1sLSiSOkYJIgdtmEyqYVIH/Y8ltLr1R8Lrjd+MmQ5VpgoGVeBF0C8u3sl5eL8Mv7qrThaXsP vHHJ603FnCSFXeYllWvE7mXeyxkUoTU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150028 On 6/9/2026 6:58 PM, Konrad Dybcio wrote: > On 6/2/26 5:21 PM, Taniya Das wrote: >> Add pinctrl states for the GP M/N divider clock output pin across >> multiple Qualcomm SoCs: >> >> wire it to the GP M/N clock controller node via pinctrl-0. >> - kodiak (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). >> - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). >> - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). >> >> Signed-off-by: Taniya Das >> --- > > Please squash the pinctrl addition and clock controller node addition > patches together (single logical change), and separate them per-platform Sure Konrad, will take care. -- Thanks, Taniya Das