Re: [PATCH v2 4/9] clk: samsung: exynos850: Style fixes

[Chanwoo Choi <cwchoi00@gmail.com>]

On 22. 8. 9. 20:33, Sam Protsenko wrote:
> Fix some typos in comments and do small coding style improvements.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> Changes in v2:
>   - (none)
> 
>  drivers/clk/samsung/clk-exynos850.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index cd9725f1dbf7..ef32546d3090 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -173,7 +173,6 @@ PNAME(mout_peri_uart_p)		= { "oscclk", "dout_shared0_div4",
>  				    "dout_shared1_div4", "oscclk" };
>  PNAME(mout_peri_ip_p)		= { "oscclk", "dout_shared0_div4",
>  				    "dout_shared1_div4", "oscclk" };
> -
>  /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
>  PNAME(mout_dpu_p)		= { "dout_shared0_div3", "dout_shared1_div3",
>  				    "dout_shared0_div4", "dout_shared1_div4" };
> @@ -599,7 +598,7 @@ static const unsigned long hsi_clk_regs[] __initconst = {
>  	CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
>  };
>  
> -/* List of parent clocks for Muxes in CMU_PERI */
> +/* List of parent clocks for Muxes in CMU_HSI */
>  PNAME(mout_hsi_bus_user_p)	= { "oscclk", "dout_hsi_bus" };
>  PNAME(mout_hsi_mmc_card_user_p)	= { "oscclk", "dout_hsi_mmc_card" };
>  PNAME(mout_hsi_usb20drd_user_p)	= { "oscclk", "dout_hsi_usb20drd" };
> @@ -963,7 +962,7 @@ static const unsigned long dpu_clk_regs[] __initconst = {
>  	CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
>  };
>  
> -/* List of parent clocks for Muxes in CMU_CORE */
> +/* List of parent clocks for Muxes in CMU_DPU */
>  PNAME(mout_dpu_user_p)		= { "oscclk", "dout_dpu" };
>  
>  static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi