* [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
[not found] <20230110175605.1240188-1-konrad.dybcio@linaro.org>
@ 2023-01-10 17:56 ` Konrad Dybcio
2023-01-10 18:54 ` Konrad Dybcio
2023-01-11 1:34 ` Rob Herring
2023-01-10 17:56 ` [PATCH v8 2/5] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio
2023-01-10 17:56 ` [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio
2 siblings, 2 replies; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-10 17:56 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno, Konrad Dybcio,
AngeloGioacchino Del Regno, Rob Herring, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Add the bindings for the CPR3 driver to the documentation.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Konrad: Add type reference to acc-syscon; update AGdR's email]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++
1 file changed, 242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
new file mode 100644
index 000000000000..52e87061a04b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
@@ -0,0 +1,242 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
+
+description: |
+ CPR (Core Power Reduction) is a technology to reduce core power on a CPU
+ or other device. Each OPP of a device corresponds to a "corner" that has
+ a range of valid voltages for a particular frequency. While the device is
+ running at a particular frequency, CPR monitors dynamic factors such as
+ temperature, etc. and suggests or, in the CPR-Hardened case performs,
+ adjustments to the voltage to save power and meet silicon characteristic
+ requirements.
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: CPRv3 controller
+ items:
+ - const: qcom,cpr3
+ - description: CPRv4 controller
+ items:
+ - const: qcom,cpr4
+ - description: CPRv4-Hardened controller
+ items:
+ - enum:
+ - qcom,msm8998-cprh
+ - qcom,sdm630-cprh
+ - const: qcom,cprh
+
+ reg:
+ description: Base address and size of the CPR controller(s)
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: "ref"
+
+ clocks:
+ items:
+ - description: CPR reference clock
+
+ vdd-supply:
+ description: Autonomous Phase Control (APC) or other power supply
+
+ '#power-domain-cells':
+ const: 1
+
+ acc-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to syscon for writing ACC settings
+
+ nvmem-cells:
+ description: Cells containing the fuse corners and revision data
+ minItems: 10
+ maxItems: 32
+
+ nvmem-cell-names:
+ minItems: 10
+ maxItems: 32
+
+ operating-points-v2: true
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - "#power-domain-cells"
+ - nvmem-cells
+ - nvmem-cell-names
+ - operating-points-v2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,kryo280";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
+ };
+
+ cpu@100 {
+ compatible = "qcom,kryo280";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
+ };
+ };
+
+ cpu_gold_opp_table: opp-table-gold {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ required-opps = <&cprh_opp3>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ required-opps = <&cprh_opp2>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cpu_silver_opp_table: opp-table-silver {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ required-opps = <&cprh_opp3>;
+ };
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cprh_opp2>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cprh_opp_table: opp-table-cprh {
+ compatible = "operating-points-v2-qcom-level";
+
+ cprh_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+ cprh_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+ cprh_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <2 3>;
+ };
+ };
+
+ apc_cprh: power-controller@179c8000 {
+ compatible = "qcom,msm8998-cprh", "qcom,cprh";
+ reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
+ clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "ref";
+
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&cprh_opp_table>;
+
+ nvmem-cells = <&cpr_efuse_speedbin>,
+ <&cpr_fuse_revision>,
+ <&cpr_quot0_pwrcl>,
+ <&cpr_quot1_pwrcl>,
+ <&cpr_quot2_pwrcl>,
+ <&cpr_quot3_pwrcl>,
+ <&cpr_quot_offset1_pwrcl>,
+ <&cpr_quot_offset2_pwrcl>,
+ <&cpr_quot_offset3_pwrcl>,
+ <&cpr_init_voltage0_pwrcl>,
+ <&cpr_init_voltage1_pwrcl>,
+ <&cpr_init_voltage2_pwrcl>,
+ <&cpr_init_voltage3_pwrcl>,
+ <&cpr_ro_sel0_pwrcl>,
+ <&cpr_ro_sel1_pwrcl>,
+ <&cpr_ro_sel2_pwrcl>,
+ <&cpr_ro_sel3_pwrcl>,
+ <&cpr_quot0_perfcl>,
+ <&cpr_quot1_perfcl>,
+ <&cpr_quot2_perfcl>,
+ <&cpr_quot3_perfcl>,
+ <&cpr_quot_offset1_perfcl>,
+ <&cpr_quot_offset2_perfcl>,
+ <&cpr_quot_offset3_perfcl>,
+ <&cpr_init_voltage0_perfcl>,
+ <&cpr_init_voltage1_perfcl>,
+ <&cpr_init_voltage2_perfcl>,
+ <&cpr_init_voltage3_perfcl>,
+ <&cpr_ro_sel0_perfcl>,
+ <&cpr_ro_sel1_perfcl>,
+ <&cpr_ro_sel2_perfcl>,
+ <&cpr_ro_sel3_perfcl>;
+
+ nvmem-cell-names = "cpr_speed_bin",
+ "cpr_fuse_revision",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_quotient4",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_quotient_offset4",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_init_voltage4",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_ring_osc4",
+ "cpr1_quotient1",
+ "cpr1_quotient2",
+ "cpr1_quotient3",
+ "cpr1_quotient4",
+ "cpr1_quotient_offset2",
+ "cpr1_quotient_offset3",
+ "cpr1_quotient_offset4",
+ "cpr1_init_voltage1",
+ "cpr1_init_voltage2",
+ "cpr1_init_voltage3",
+ "cpr1_init_voltage4",
+ "cpr1_ring_osc1",
+ "cpr1_ring_osc2",
+ "cpr1_ring_osc3",
+ "cpr1_ring_osc4";
+ };
+...
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
2023-01-10 17:56 ` [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
@ 2023-01-10 18:54 ` Konrad Dybcio
2023-01-11 2:18 ` Dmitry Baryshkov
2023-01-11 1:34 ` Rob Herring
1 sibling, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-10 18:54 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno,
AngeloGioacchino Del Regno, Rob Herring, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
On 10.01.2023 18:56, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>
> Add the bindings for the CPR3 driver to the documentation.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> [Konrad: Add type reference to acc-syscon; update AGdR's email]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
Need to add
qcom,opp-oloop-vadj
qcom,opp-cloop-vadj
in next revision.
Konrad
> .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++
> 1 file changed, 242 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
> new file mode 100644
> index 000000000000..52e87061a04b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
> @@ -0,0 +1,242 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
> +
> +description: |
> + CPR (Core Power Reduction) is a technology to reduce core power on a CPU
> + or other device. Each OPP of a device corresponds to a "corner" that has
> + a range of valid voltages for a particular frequency. While the device is
> + running at a particular frequency, CPR monitors dynamic factors such as
> + temperature, etc. and suggests or, in the CPR-Hardened case performs,
> + adjustments to the voltage to save power and meet silicon characteristic
> + requirements.
> +
> +maintainers:
> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: CPRv3 controller
> + items:
> + - const: qcom,cpr3
> + - description: CPRv4 controller
> + items:
> + - const: qcom,cpr4
> + - description: CPRv4-Hardened controller
> + items:
> + - enum:
> + - qcom,msm8998-cprh
> + - qcom,sdm630-cprh
> + - const: qcom,cprh
> +
> + reg:
> + description: Base address and size of the CPR controller(s)
> + minItems: 1
> + maxItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: "ref"
> +
> + clocks:
> + items:
> + - description: CPR reference clock
> +
> + vdd-supply:
> + description: Autonomous Phase Control (APC) or other power supply
> +
> + '#power-domain-cells':
> + const: 1
> +
> + acc-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle to syscon for writing ACC settings
> +
> + nvmem-cells:
> + description: Cells containing the fuse corners and revision data
> + minItems: 10
> + maxItems: 32
> +
> + nvmem-cell-names:
> + minItems: 10
> + maxItems: 32
> +
> + operating-points-v2: true
> +
> +required:
> + - compatible
> + - reg
> + - clock-names
> + - clocks
> + - "#power-domain-cells"
> + - nvmem-cells
> + - nvmem-cell-names
> + - operating-points-v2
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-msm8998.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "qcom,kryo280";
> + device_type = "cpu";
> + reg = <0x0 0x0>;
> + operating-points-v2 = <&cpu_gold_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
> + };
> +
> + cpu@100 {
> + compatible = "qcom,kryo280";
> + device_type = "cpu";
> + reg = <0x0 0x0>;
> + operating-points-v2 = <&cpu_silver_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> + };
> + };
> +
> + cpu_gold_opp_table: opp-table-gold {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-2208000000 {
> + opp-hz = /bits/ 64 <2208000000>;
> + required-opps = <&cprh_opp3>;
> + };
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + required-opps = <&cprh_opp2>;
> + };
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cpu_silver_opp_table: opp-table-silver {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + required-opps = <&cprh_opp3>;
> + };
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + required-opps = <&cprh_opp2>;
> + };
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cprh_opp_table: opp-table-cprh {
> + compatible = "operating-points-v2-qcom-level";
> +
> + cprh_opp1: opp1 {
> + opp-level = <1>;
> + qcom,opp-fuse-level = <1>;
> + };
> + cprh_opp2: opp2 {
> + opp-level = <2>;
> + qcom,opp-fuse-level = <2>;
> + };
> + cprh_opp3: opp3 {
> + opp-level = <3>;
> + qcom,opp-fuse-level = <2 3>;
> + };
> + };
> +
> + apc_cprh: power-controller@179c8000 {
> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
> + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
> + clock-names = "ref";
> +
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&cprh_opp_table>;
> +
> + nvmem-cells = <&cpr_efuse_speedbin>,
> + <&cpr_fuse_revision>,
> + <&cpr_quot0_pwrcl>,
> + <&cpr_quot1_pwrcl>,
> + <&cpr_quot2_pwrcl>,
> + <&cpr_quot3_pwrcl>,
> + <&cpr_quot_offset1_pwrcl>,
> + <&cpr_quot_offset2_pwrcl>,
> + <&cpr_quot_offset3_pwrcl>,
> + <&cpr_init_voltage0_pwrcl>,
> + <&cpr_init_voltage1_pwrcl>,
> + <&cpr_init_voltage2_pwrcl>,
> + <&cpr_init_voltage3_pwrcl>,
> + <&cpr_ro_sel0_pwrcl>,
> + <&cpr_ro_sel1_pwrcl>,
> + <&cpr_ro_sel2_pwrcl>,
> + <&cpr_ro_sel3_pwrcl>,
> + <&cpr_quot0_perfcl>,
> + <&cpr_quot1_perfcl>,
> + <&cpr_quot2_perfcl>,
> + <&cpr_quot3_perfcl>,
> + <&cpr_quot_offset1_perfcl>,
> + <&cpr_quot_offset2_perfcl>,
> + <&cpr_quot_offset3_perfcl>,
> + <&cpr_init_voltage0_perfcl>,
> + <&cpr_init_voltage1_perfcl>,
> + <&cpr_init_voltage2_perfcl>,
> + <&cpr_init_voltage3_perfcl>,
> + <&cpr_ro_sel0_perfcl>,
> + <&cpr_ro_sel1_perfcl>,
> + <&cpr_ro_sel2_perfcl>,
> + <&cpr_ro_sel3_perfcl>;
> +
> + nvmem-cell-names = "cpr_speed_bin",
> + "cpr_fuse_revision",
> + "cpr0_quotient1",
> + "cpr0_quotient2",
> + "cpr0_quotient3",
> + "cpr0_quotient4",
> + "cpr0_quotient_offset2",
> + "cpr0_quotient_offset3",
> + "cpr0_quotient_offset4",
> + "cpr0_init_voltage1",
> + "cpr0_init_voltage2",
> + "cpr0_init_voltage3",
> + "cpr0_init_voltage4",
> + "cpr0_ring_osc1",
> + "cpr0_ring_osc2",
> + "cpr0_ring_osc3",
> + "cpr0_ring_osc4",
> + "cpr1_quotient1",
> + "cpr1_quotient2",
> + "cpr1_quotient3",
> + "cpr1_quotient4",
> + "cpr1_quotient_offset2",
> + "cpr1_quotient_offset3",
> + "cpr1_quotient_offset4",
> + "cpr1_init_voltage1",
> + "cpr1_init_voltage2",
> + "cpr1_init_voltage3",
> + "cpr1_init_voltage4",
> + "cpr1_ring_osc1",
> + "cpr1_ring_osc2",
> + "cpr1_ring_osc3",
> + "cpr1_ring_osc4";
> + };
> +...
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
2023-01-10 18:54 ` Konrad Dybcio
@ 2023-01-11 2:18 ` Dmitry Baryshkov
2023-01-11 13:30 ` Konrad Dybcio
0 siblings, 1 reply; 10+ messages in thread
From: Dmitry Baryshkov @ 2023-01-11 2:18 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno,
AngeloGioacchino Del Regno, Rob Herring, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
On 10/01/2023 20:54, Konrad Dybcio wrote:
>
>
> On 10.01.2023 18:56, Konrad Dybcio wrote:
>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>
>> Add the bindings for the CPR3 driver to the documentation.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>> [Konrad: Add type reference to acc-syscon; update AGdR's email]
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
> Need to add
>
> qcom,opp-oloop-vadj
> qcom,opp-cloop-vadj
And note that at least for CPR3 they are different between fusing
revisions. I see that for CPRh (esp. for 8998v2) they are the same, but
this is not the case for 8996 (CPR3).
>
> in next revision.
>
> Konrad
>> .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++
>> 1 file changed, 242 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>> new file mode 100644
>> index 000000000000..52e87061a04b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>> @@ -0,0 +1,242 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
>> +
>> +description: |
>> + CPR (Core Power Reduction) is a technology to reduce core power on a CPU
>> + or other device. Each OPP of a device corresponds to a "corner" that has
>> + a range of valid voltages for a particular frequency. While the device is
>> + running at a particular frequency, CPR monitors dynamic factors such as
>> + temperature, etc. and suggests or, in the CPR-Hardened case performs,
>> + adjustments to the voltage to save power and meet silicon characteristic
>> + requirements.
>> +
>> +maintainers:
>> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - description: CPRv3 controller
>> + items:
>> + - const: qcom,cpr3
>> + - description: CPRv4 controller
>> + items:
>> + - const: qcom,cpr4
>> + - description: CPRv4-Hardened controller
>> + items:
>> + - enum:
>> + - qcom,msm8998-cprh
>> + - qcom,sdm630-cprh
>> + - const: qcom,cprh
>> +
>> + reg:
>> + description: Base address and size of the CPR controller(s)
>> + minItems: 1
>> + maxItems: 2
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: "ref"
>> +
>> + clocks:
>> + items:
>> + - description: CPR reference clock
>> +
>> + vdd-supply:
>> + description: Autonomous Phase Control (APC) or other power supply
>> +
>> + '#power-domain-cells':
>> + const: 1
>> +
>> + acc-syscon:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: phandle to syscon for writing ACC settings
>> +
>> + nvmem-cells:
>> + description: Cells containing the fuse corners and revision data
>> + minItems: 10
>> + maxItems: 32
>> +
>> + nvmem-cell-names:
>> + minItems: 10
>> + maxItems: 32
>> +
>> + operating-points-v2: true
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clock-names
>> + - clocks
>> + - "#power-domain-cells"
>> + - nvmem-cells
>> + - nvmem-cell-names
>> + - operating-points-v2
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,gcc-msm8998.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "qcom,kryo280";
>> + device_type = "cpu";
>> + reg = <0x0 0x0>;
>> + operating-points-v2 = <&cpu_gold_opp_table>;
>> + power-domains = <&apc_cprh 0>;
>> + power-domain-names = "cprh";
>> + };
>> +
>> + cpu@100 {
>> + compatible = "qcom,kryo280";
>> + device_type = "cpu";
>> + reg = <0x0 0x0>;
>> + operating-points-v2 = <&cpu_silver_opp_table>;
>> + power-domains = <&apc_cprh 1>;
>> + power-domain-names = "cprh";
>> + };
>> + };
>> +
>> + cpu_gold_opp_table: opp-table-gold {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-2208000000 {
>> + opp-hz = /bits/ 64 <2208000000>;
>> + required-opps = <&cprh_opp3>;
>> + };
>> + opp-1113600000 {
>> + opp-hz = /bits/ 64 <1113600000>;
>> + required-opps = <&cprh_opp2>;
>> + };
>> + opp-300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + required-opps = <&cprh_opp1>;
>> + };
>> + };
>> +
>> + cpu_silver_opp_table: opp-table-silver {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-1843200000 {
>> + opp-hz = /bits/ 64 <1843200000>;
>> + required-opps = <&cprh_opp3>;
>> + };
>> + opp-1094400000 {
>> + opp-hz = /bits/ 64 <1094400000>;
>> + required-opps = <&cprh_opp2>;
>> + };
>> + opp-300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + required-opps = <&cprh_opp1>;
>> + };
>> + };
>> +
>> + cprh_opp_table: opp-table-cprh {
>> + compatible = "operating-points-v2-qcom-level";
>> +
>> + cprh_opp1: opp1 {
>> + opp-level = <1>;
>> + qcom,opp-fuse-level = <1>;
>> + };
>> + cprh_opp2: opp2 {
>> + opp-level = <2>;
>> + qcom,opp-fuse-level = <2>;
>> + };
>> + cprh_opp3: opp3 {
>> + opp-level = <3>;
>> + qcom,opp-fuse-level = <2 3>;
>> + };
>> + };
>> +
>> + apc_cprh: power-controller@179c8000 {
>> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
>> + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
>> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
>> + clock-names = "ref";
>> +
>> + #power-domain-cells = <1>;
>> + operating-points-v2 = <&cprh_opp_table>;
>> +
>> + nvmem-cells = <&cpr_efuse_speedbin>,
>> + <&cpr_fuse_revision>,
>> + <&cpr_quot0_pwrcl>,
>> + <&cpr_quot1_pwrcl>,
>> + <&cpr_quot2_pwrcl>,
>> + <&cpr_quot3_pwrcl>,
>> + <&cpr_quot_offset1_pwrcl>,
>> + <&cpr_quot_offset2_pwrcl>,
>> + <&cpr_quot_offset3_pwrcl>,
>> + <&cpr_init_voltage0_pwrcl>,
>> + <&cpr_init_voltage1_pwrcl>,
>> + <&cpr_init_voltage2_pwrcl>,
>> + <&cpr_init_voltage3_pwrcl>,
>> + <&cpr_ro_sel0_pwrcl>,
>> + <&cpr_ro_sel1_pwrcl>,
>> + <&cpr_ro_sel2_pwrcl>,
>> + <&cpr_ro_sel3_pwrcl>,
>> + <&cpr_quot0_perfcl>,
>> + <&cpr_quot1_perfcl>,
>> + <&cpr_quot2_perfcl>,
>> + <&cpr_quot3_perfcl>,
>> + <&cpr_quot_offset1_perfcl>,
>> + <&cpr_quot_offset2_perfcl>,
>> + <&cpr_quot_offset3_perfcl>,
>> + <&cpr_init_voltage0_perfcl>,
>> + <&cpr_init_voltage1_perfcl>,
>> + <&cpr_init_voltage2_perfcl>,
>> + <&cpr_init_voltage3_perfcl>,
>> + <&cpr_ro_sel0_perfcl>,
>> + <&cpr_ro_sel1_perfcl>,
>> + <&cpr_ro_sel2_perfcl>,
>> + <&cpr_ro_sel3_perfcl>;
>> +
>> + nvmem-cell-names = "cpr_speed_bin",
>> + "cpr_fuse_revision",
>> + "cpr0_quotient1",
>> + "cpr0_quotient2",
>> + "cpr0_quotient3",
>> + "cpr0_quotient4",
>> + "cpr0_quotient_offset2",
>> + "cpr0_quotient_offset3",
>> + "cpr0_quotient_offset4",
>> + "cpr0_init_voltage1",
>> + "cpr0_init_voltage2",
>> + "cpr0_init_voltage3",
>> + "cpr0_init_voltage4",
>> + "cpr0_ring_osc1",
>> + "cpr0_ring_osc2",
>> + "cpr0_ring_osc3",
>> + "cpr0_ring_osc4",
>> + "cpr1_quotient1",
>> + "cpr1_quotient2",
>> + "cpr1_quotient3",
>> + "cpr1_quotient4",
>> + "cpr1_quotient_offset2",
>> + "cpr1_quotient_offset3",
>> + "cpr1_quotient_offset4",
>> + "cpr1_init_voltage1",
>> + "cpr1_init_voltage2",
>> + "cpr1_init_voltage3",
>> + "cpr1_init_voltage4",
>> + "cpr1_ring_osc1",
>> + "cpr1_ring_osc2",
>> + "cpr1_ring_osc3",
>> + "cpr1_ring_osc4";
>> + };
>> +...
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
2023-01-11 2:18 ` Dmitry Baryshkov
@ 2023-01-11 13:30 ` Konrad Dybcio
2023-01-11 15:58 ` Dmitry Baryshkov
0 siblings, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-11 13:30 UTC (permalink / raw)
To: Dmitry Baryshkov, linux-arm-msm, andersson, agross,
krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno,
AngeloGioacchino Del Regno, Rob Herring, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
On 11.01.2023 03:18, Dmitry Baryshkov wrote:
> On 10/01/2023 20:54, Konrad Dybcio wrote:
>>
>>
>> On 10.01.2023 18:56, Konrad Dybcio wrote:
>>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>>
>>> Add the bindings for the CPR3 driver to the documentation.
>>>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>> [Konrad: Add type reference to acc-syscon; update AGdR's email]
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>> Need to add
>>
>> qcom,opp-oloop-vadj
>> qcom,opp-cloop-vadj
>
> And note that at least for CPR3 they are different between fusing revisions. I see that for CPRh (esp. for 8998v2) they are the same, but this is not the case for 8996 (CPR3).
If we both mean the "speed bin"-dependent values, the driver
reads the fuse value but currently does nothing. My guess would
be that Angelo omitted it, as - just like you pointed out - MSM8998
(and SDM660 for that matter) don't really use it. I suppose I could
take care of that in bindings by making this an array and handle it
separately in a different patchset, as the per-revision values
aren't *that much* different, and again aren't really of concern for
the first round of supported SoCs.
Konrad
>
>>
>> in next revision.
>>
>> Konrad
>>> .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++
>>> 1 file changed, 242 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>>> new file mode 100644
>>> index 000000000000..52e87061a04b
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>>> @@ -0,0 +1,242 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
>>> +
>>> +description: |
>>> + CPR (Core Power Reduction) is a technology to reduce core power on a CPU
>>> + or other device. Each OPP of a device corresponds to a "corner" that has
>>> + a range of valid voltages for a particular frequency. While the device is
>>> + running at a particular frequency, CPR monitors dynamic factors such as
>>> + temperature, etc. and suggests or, in the CPR-Hardened case performs,
>>> + adjustments to the voltage to save power and meet silicon characteristic
>>> + requirements.
>>> +
>>> +maintainers:
>>> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + oneOf:
>>> + - description: CPRv3 controller
>>> + items:
>>> + - const: qcom,cpr3
>>> + - description: CPRv4 controller
>>> + items:
>>> + - const: qcom,cpr4
>>> + - description: CPRv4-Hardened controller
>>> + items:
>>> + - enum:
>>> + - qcom,msm8998-cprh
>>> + - qcom,sdm630-cprh
>>> + - const: qcom,cprh
>>> +
>>> + reg:
>>> + description: Base address and size of the CPR controller(s)
>>> + minItems: 1
>>> + maxItems: 2
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: "ref"
>>> +
>>> + clocks:
>>> + items:
>>> + - description: CPR reference clock
>>> +
>>> + vdd-supply:
>>> + description: Autonomous Phase Control (APC) or other power supply
>>> +
>>> + '#power-domain-cells':
>>> + const: 1
>>> +
>>> + acc-syscon:
>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>> + description: phandle to syscon for writing ACC settings
>>> +
>>> + nvmem-cells:
>>> + description: Cells containing the fuse corners and revision data
>>> + minItems: 10
>>> + maxItems: 32
>>> +
>>> + nvmem-cell-names:
>>> + minItems: 10
>>> + maxItems: 32
>>> +
>>> + operating-points-v2: true
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - clock-names
>>> + - clocks
>>> + - "#power-domain-cells"
>>> + - nvmem-cells
>>> + - nvmem-cell-names
>>> + - operating-points-v2
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/clock/qcom,gcc-msm8998.h>
>>> + #include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> + cpus {
>>> + #address-cells = <2>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu@0 {
>>> + compatible = "qcom,kryo280";
>>> + device_type = "cpu";
>>> + reg = <0x0 0x0>;
>>> + operating-points-v2 = <&cpu_gold_opp_table>;
>>> + power-domains = <&apc_cprh 0>;
>>> + power-domain-names = "cprh";
>>> + };
>>> +
>>> + cpu@100 {
>>> + compatible = "qcom,kryo280";
>>> + device_type = "cpu";
>>> + reg = <0x0 0x0>;
>>> + operating-points-v2 = <&cpu_silver_opp_table>;
>>> + power-domains = <&apc_cprh 1>;
>>> + power-domain-names = "cprh";
>>> + };
>>> + };
>>> +
>>> + cpu_gold_opp_table: opp-table-gold {
>>> + compatible = "operating-points-v2";
>>> + opp-shared;
>>> +
>>> + opp-2208000000 {
>>> + opp-hz = /bits/ 64 <2208000000>;
>>> + required-opps = <&cprh_opp3>;
>>> + };
>>> + opp-1113600000 {
>>> + opp-hz = /bits/ 64 <1113600000>;
>>> + required-opps = <&cprh_opp2>;
>>> + };
>>> + opp-300000000 {
>>> + opp-hz = /bits/ 64 <300000000>;
>>> + required-opps = <&cprh_opp1>;
>>> + };
>>> + };
>>> +
>>> + cpu_silver_opp_table: opp-table-silver {
>>> + compatible = "operating-points-v2";
>>> + opp-shared;
>>> +
>>> + opp-1843200000 {
>>> + opp-hz = /bits/ 64 <1843200000>;
>>> + required-opps = <&cprh_opp3>;
>>> + };
>>> + opp-1094400000 {
>>> + opp-hz = /bits/ 64 <1094400000>;
>>> + required-opps = <&cprh_opp2>;
>>> + };
>>> + opp-300000000 {
>>> + opp-hz = /bits/ 64 <300000000>;
>>> + required-opps = <&cprh_opp1>;
>>> + };
>>> + };
>>> +
>>> + cprh_opp_table: opp-table-cprh {
>>> + compatible = "operating-points-v2-qcom-level";
>>> +
>>> + cprh_opp1: opp1 {
>>> + opp-level = <1>;
>>> + qcom,opp-fuse-level = <1>;
>>> + };
>>> + cprh_opp2: opp2 {
>>> + opp-level = <2>;
>>> + qcom,opp-fuse-level = <2>;
>>> + };
>>> + cprh_opp3: opp3 {
>>> + opp-level = <3>;
>>> + qcom,opp-fuse-level = <2 3>;
>>> + };
>>> + };
>>> +
>>> + apc_cprh: power-controller@179c8000 {
>>> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
>>> + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
>>> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
>>> + clock-names = "ref";
>>> +
>>> + #power-domain-cells = <1>;
>>> + operating-points-v2 = <&cprh_opp_table>;
>>> +
>>> + nvmem-cells = <&cpr_efuse_speedbin>,
>>> + <&cpr_fuse_revision>,
>>> + <&cpr_quot0_pwrcl>,
>>> + <&cpr_quot1_pwrcl>,
>>> + <&cpr_quot2_pwrcl>,
>>> + <&cpr_quot3_pwrcl>,
>>> + <&cpr_quot_offset1_pwrcl>,
>>> + <&cpr_quot_offset2_pwrcl>,
>>> + <&cpr_quot_offset3_pwrcl>,
>>> + <&cpr_init_voltage0_pwrcl>,
>>> + <&cpr_init_voltage1_pwrcl>,
>>> + <&cpr_init_voltage2_pwrcl>,
>>> + <&cpr_init_voltage3_pwrcl>,
>>> + <&cpr_ro_sel0_pwrcl>,
>>> + <&cpr_ro_sel1_pwrcl>,
>>> + <&cpr_ro_sel2_pwrcl>,
>>> + <&cpr_ro_sel3_pwrcl>,
>>> + <&cpr_quot0_perfcl>,
>>> + <&cpr_quot1_perfcl>,
>>> + <&cpr_quot2_perfcl>,
>>> + <&cpr_quot3_perfcl>,
>>> + <&cpr_quot_offset1_perfcl>,
>>> + <&cpr_quot_offset2_perfcl>,
>>> + <&cpr_quot_offset3_perfcl>,
>>> + <&cpr_init_voltage0_perfcl>,
>>> + <&cpr_init_voltage1_perfcl>,
>>> + <&cpr_init_voltage2_perfcl>,
>>> + <&cpr_init_voltage3_perfcl>,
>>> + <&cpr_ro_sel0_perfcl>,
>>> + <&cpr_ro_sel1_perfcl>,
>>> + <&cpr_ro_sel2_perfcl>,
>>> + <&cpr_ro_sel3_perfcl>;
>>> +
>>> + nvmem-cell-names = "cpr_speed_bin",
>>> + "cpr_fuse_revision",
>>> + "cpr0_quotient1",
>>> + "cpr0_quotient2",
>>> + "cpr0_quotient3",
>>> + "cpr0_quotient4",
>>> + "cpr0_quotient_offset2",
>>> + "cpr0_quotient_offset3",
>>> + "cpr0_quotient_offset4",
>>> + "cpr0_init_voltage1",
>>> + "cpr0_init_voltage2",
>>> + "cpr0_init_voltage3",
>>> + "cpr0_init_voltage4",
>>> + "cpr0_ring_osc1",
>>> + "cpr0_ring_osc2",
>>> + "cpr0_ring_osc3",
>>> + "cpr0_ring_osc4",
>>> + "cpr1_quotient1",
>>> + "cpr1_quotient2",
>>> + "cpr1_quotient3",
>>> + "cpr1_quotient4",
>>> + "cpr1_quotient_offset2",
>>> + "cpr1_quotient_offset3",
>>> + "cpr1_quotient_offset4",
>>> + "cpr1_init_voltage1",
>>> + "cpr1_init_voltage2",
>>> + "cpr1_init_voltage3",
>>> + "cpr1_init_voltage4",
>>> + "cpr1_ring_osc1",
>>> + "cpr1_ring_osc2",
>>> + "cpr1_ring_osc3",
>>> + "cpr1_ring_osc4";
>>> + };
>>> +...
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
2023-01-11 13:30 ` Konrad Dybcio
@ 2023-01-11 15:58 ` Dmitry Baryshkov
0 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2023-01-11 15:58 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno,
AngeloGioacchino Del Regno, Rob Herring, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
On 11/01/2023 15:30, Konrad Dybcio wrote:
>
>
> On 11.01.2023 03:18, Dmitry Baryshkov wrote:
>> On 10/01/2023 20:54, Konrad Dybcio wrote:
>>>
>>>
>>> On 10.01.2023 18:56, Konrad Dybcio wrote:
>>>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>>>
>>>> Add the bindings for the CPR3 driver to the documentation.
>>>>
>>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>>> [Konrad: Add type reference to acc-syscon; update AGdR's email]
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>>> Need to add
>>>
>>> qcom,opp-oloop-vadj
>>> qcom,opp-cloop-vadj
>>
>> And note that at least for CPR3 they are different between fusing revisions. I see that for CPRh (esp. for 8998v2) they are the same, but this is not the case for 8996 (CPR3).
> If we both mean the "speed bin"-dependent values, the driver
> reads the fuse value but currently does nothing. My guess would
> be that Angelo omitted it, as - just like you pointed out - MSM8998
> (and SDM660 for that matter) don't really use it. I suppose I could
> take care of that in bindings by making this an array and handle it
> separately in a different patchset, as the per-revision values
> aren't *that much* different, and again aren't really of concern for
> the first round of supported SoCs.
No, there are two dimensions there: speed-bin and then cpr fusing_rev, see:
ret = nvmem_cell_read_variable_le_u32(dev, "cpr_fuse_revision",
&drv->fusing_rev);
While the speed bin determines overall SoC performance characteristics,
cpr_fuse_revision determines how we interpret the fuse values. E.g. on
msm8996 some of loop adjustment values depend on fusing_rev. I
interpreted this as 'the manufacturer could not decide on how to measure
things'. May be we can support only the latest fusing rev (like we do
for the SoC versions). But I can not guarantee that it would be enough.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
2023-01-10 17:56 ` [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
2023-01-10 18:54 ` Konrad Dybcio
@ 2023-01-11 1:34 ` Rob Herring
1 sibling, 0 replies; 10+ messages in thread
From: Rob Herring @ 2023-01-11 1:34 UTC (permalink / raw)
To: Konrad Dybcio
Cc: marijn.suijten, linux-kernel, AngeloGioacchino Del Regno,
krzysztof.kozlowski, angelogioacchino.delregno, agross, andersson,
Krzysztof Kozlowski, devicetree, linux-arm-msm, Rob Herring
On Tue, 10 Jan 2023 18:56:01 +0100, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>
> Add the bindings for the CPR3 driver to the documentation.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> [Konrad: Add type reference to acc-syscon; update AGdR's email]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++
> 1 file changed, 242 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp3:qcom,opp-fuse-level:0: [2, 3] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230110175605.1240188-2-konrad.dybcio@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 2/5] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array
[not found] <20230110175605.1240188-1-konrad.dybcio@linaro.org>
2023-01-10 17:56 ` [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
@ 2023-01-10 17:56 ` Konrad Dybcio
2023-01-13 1:26 ` Rob Herring
2023-01-10 17:56 ` [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio
2 siblings, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-10 17:56 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno, Konrad Dybcio,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Niklas Cassel, linux-pm, devicetree,
linux-kernel
In some instances (particularly with CPRh) we might want to specifiy
more than one qcom,opp-fuse-level, as the same OPP subnodes may be
used by different "CPR threads". We need to make sure that
n = num_threads entries is legal and so far nobody seems to use more
than two, so let's allow that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
index b9ce2e099ce9..a30ef93213c0 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
@@ -30,7 +30,9 @@ patternProperties:
this OPP node. Sometimes several corners/levels shares a certain fuse
corner/level. A fuse corner/level contains e.g. ref uV, min uV,
and max uV.
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
required:
- opp-level
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v8 2/5] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array
2023-01-10 17:56 ` [PATCH v8 2/5] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio
@ 2023-01-13 1:26 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2023-01-13 1:26 UTC (permalink / raw)
To: Konrad Dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-pm, marijn.suijten,
devicetree, andersson, agross, krzysztof.kozlowski,
angelogioacchino.delregno, Rob Herring, linux-kernel,
Viresh Kumar, Nishanth Menon, Niklas Cassel, Stephen Boyd
On Tue, 10 Jan 2023 18:56:02 +0100, Konrad Dybcio wrote:
> In some instances (particularly with CPRh) we might want to specifiy
> more than one qcom,opp-fuse-level, as the same OPP subnodes may be
> used by different "CPR threads". We need to make sure that
> n = num_threads entries is legal and so far nobody seems to use more
> than two, so let's allow that.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh
[not found] <20230110175605.1240188-1-konrad.dybcio@linaro.org>
2023-01-10 17:56 ` [PATCH v8 1/5] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
2023-01-10 17:56 ` [PATCH v8 2/5] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio
@ 2023-01-10 17:56 ` Konrad Dybcio
2023-01-10 18:45 ` Konrad Dybcio
2 siblings, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-10 17:56 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno, Konrad Dybcio,
AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Now that the CPR v3/v4/Hardened is ready, enable it on MSM8998.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Konrad: separate from adding cpufreq, sort nodes and use lowercase hex]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 325 ++++++++++++++++++++++++++
1 file changed, 325 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index af29a4bfd109..84f73484441f 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -139,6 +139,9 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -153,6 +156,9 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU2: cpu@2 {
@@ -163,6 +169,9 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU3: cpu@3 {
@@ -173,6 +182,9 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU4: cpu@100 {
@@ -183,6 +195,9 @@ CPU4: cpu@100 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -197,6 +212,9 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
CPU6: cpu@102 {
@@ -207,6 +225,9 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
CPU7: cpu@103 {
@@ -217,6 +238,9 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
cpu-map {
@@ -310,6 +334,65 @@ scm {
};
};
+ cpu_gold_opp_table: opp-table-gold {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cpu_silver_opp_table: opp-table-silver {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cprh_opp_table: opp-table-cprh {
+ compatible = "operating-points-v2-qcom-level";
+
+ cprh_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+
+ cprh_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+
+ cprh_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <2 3>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -839,6 +922,174 @@ qfprom: qfprom@784000 {
#address-cells = <1>;
#size-cells = <1>;
+ cpr_efuse_speedbin: speedbin@133 {
+ reg = <0x133 0x8>;
+ bits = <5 3>;
+ };
+
+ cpr_fuse_revision: cpr_fusing_rev@13e {
+ reg = <0x13e 0x1>;
+ bits = <3 3>;
+ };
+
+ /* CPR Ring Oscillator: Power Cluster */
+ cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 {
+ reg = <0x218 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 {
+ reg = <0x218 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 {
+ reg = <0x219 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 {
+ reg = <0x219 0x1>;
+ bits = <4 4>;
+ };
+
+ /* CPR Init Voltage: Power Cluster */
+ cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a {
+ reg = <0x21a 0x1>;
+ bits = <0 6>;
+ };
+
+ cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a {
+ reg = <0x21a 0x1>;
+ bits = <6 6>;
+ };
+
+ cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b {
+ reg = <0x21b 0x1>;
+ bits = <4 6>;
+ };
+
+ cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c {
+ reg = <0x21c 0x1>;
+ bits = <2 6>;
+ };
+
+ /* CPR Target Quotients: Power Cluster */
+ cpr_quot3_pwrcl: quot3_pwrcl@21d {
+ reg = <0x21d 0x2>;
+ bits = <6 12>;
+ };
+
+ cpr_quot2_pwrcl: quot2_pwrcl@21f {
+ reg = <0x21f 0x2>;
+ bits = <2 11>;
+ };
+
+ cpr_quot1_pwrcl: quot1_pwrcl@220 {
+ reg = <0x220 0x2>;
+ bits = <6 12>;
+ };
+
+ cpr_quot0_pwrcl: quot0_pwrcl@222 {
+ reg = <0x222 0x2>;
+ bits = <2 12>;
+ };
+
+ /* CPR Quotient Offsets: Power Cluster */
+ cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 {
+ reg = <0x226 0x1>;
+ bits = <1 7>;
+ };
+
+ cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 {
+ reg = <0x227 0x1>;
+ bits = <0 7>;
+ };
+
+ cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 {
+ reg = <0x227 0x1>;
+ bits = <7 6>;
+ };
+
+ /* CPR Ring Oscillator: Performance Cluster */
+ cpr_ro_sel3_perfcl: rosel3_perfcl@229 {
+ reg = <0x229 0x1>;
+ bits = <6 4>;
+ };
+
+ cpr_ro_sel2_perfcl: rosel2_perfcl@22a {
+ reg = <0x22a 0x1>;
+ bits = <2 4>;
+ };
+
+ cpr_ro_sel1_perfcl: rosel1_perfcl@22a {
+ reg = <0x22a 0x1>;
+ bits = <6 4>;
+ };
+
+ cpr_ro_sel0_perfcl: rosel0_perfcl@22b {
+ reg = <0x22b 0x1>;
+ bits = <2 4>;
+ };
+
+ /* CPR Init Voltage: Performance Cluster */
+ cpr_init_voltage3_perfcl: ivolt3_perfcl@22b {
+ reg = <0x22b 0x1>;
+ bits = <6 6>;
+ };
+
+ cpr_init_voltage2_perfcl: ivolt2_perfcl@22c {
+ reg = <0x22c 0x1>;
+ bits = <4 6>;
+ };
+
+ cpr_init_voltage1_perfcl: ivolt1_perfcl@22d {
+ reg = <0x22d 0x1>;
+ bits = <2 6>;
+ };
+
+ cpr_init_voltage0_perfcl: ivolt0_perfcl@22e {
+ reg = <0x22e 0x1>;
+ bits = <0 6>;
+ };
+
+ /* CPR Target Quotients: Performance Cluster */
+ cpr_quot3_perfcl: quot3_perfcl@22f {
+ reg = <0x22f 0x2>;
+ bits = <4 11>;
+ };
+
+ cpr_quot2_perfcl: quot2_perfcl@231 {
+ reg = <0x231 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_quot1_perfcl: quot1_perfcl@232 {
+ reg = <0x232 0x2>;
+ bits = <4 12>;
+ };
+
+ cpr_quot0_perfcl: quot0_perfcl@234 {
+ reg = <0x234 0x2>;
+ bits = <0 12>;
+ };
+
+ /* CPR Quotient Offsets: Performance Cluster */
+ cpr_quot_offset3_perfcl: qoff3_perfcl@237 {
+ reg = <0x237 0x1>;
+ bits = <7 6>;
+ };
+
+ cpr_quot_offset2_perfcl: qoff2_perfcl@238 {
+ reg = <0x238 0x1>;
+ bits = <6 7>;
+ };
+
+ cpr_quot_offset1_perfcl: qoff1_perfcl@239 {
+ reg = <0x239 0x1>;
+ bits = <5 3>;
+ };
+
qusb2_hstx_trim: hstx-trim@23a {
reg = <0x23a 0x1>;
bits = <0 4>;
@@ -2998,6 +3249,80 @@ frame@17928000 {
};
};
+ apc_cprh: power-controller@179c8000 {
+ compatible = "qcom,msm8998-cprh", "qcom,cprh";
+ reg = <0x0179c4000 0x4000>, <0x0179c8000 0x4000>;
+ clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "ref";
+ operating-points-v2 = <&cprh_opp_table>;
+ #power-domain-cells = <1>;
+
+ nvmem-cells = <&cpr_efuse_speedbin>,
+ <&cpr_fuse_revision>,
+ <&cpr_quot0_pwrcl>,
+ <&cpr_quot1_pwrcl>,
+ <&cpr_quot2_pwrcl>,
+ <&cpr_quot3_pwrcl>,
+ <&cpr_quot_offset1_pwrcl>,
+ <&cpr_quot_offset2_pwrcl>,
+ <&cpr_quot_offset3_pwrcl>,
+ <&cpr_init_voltage0_pwrcl>,
+ <&cpr_init_voltage1_pwrcl>,
+ <&cpr_init_voltage2_pwrcl>,
+ <&cpr_init_voltage3_pwrcl>,
+ <&cpr_ro_sel0_pwrcl>,
+ <&cpr_ro_sel1_pwrcl>,
+ <&cpr_ro_sel2_pwrcl>,
+ <&cpr_ro_sel3_pwrcl>,
+ <&cpr_quot0_perfcl>,
+ <&cpr_quot1_perfcl>,
+ <&cpr_quot2_perfcl>,
+ <&cpr_quot3_perfcl>,
+ <&cpr_quot_offset1_perfcl>,
+ <&cpr_quot_offset2_perfcl>,
+ <&cpr_quot_offset3_perfcl>,
+ <&cpr_init_voltage0_perfcl>,
+ <&cpr_init_voltage1_perfcl>,
+ <&cpr_init_voltage2_perfcl>,
+ <&cpr_init_voltage3_perfcl>,
+ <&cpr_ro_sel0_perfcl>,
+ <&cpr_ro_sel1_perfcl>,
+ <&cpr_ro_sel2_perfcl>,
+ <&cpr_ro_sel3_perfcl>;
+ nvmem-cell-names = "cpr_speed_bin",
+ "cpr_fuse_revision",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_quotient4",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_quotient_offset4",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_init_voltage4",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_ring_osc4",
+ "cpr1_quotient1",
+ "cpr1_quotient2",
+ "cpr1_quotient3",
+ "cpr1_quotient4",
+ "cpr1_quotient_offset2",
+ "cpr1_quotient_offset3",
+ "cpr1_quotient_offset4",
+ "cpr1_init_voltage1",
+ "cpr1_init_voltage2",
+ "cpr1_init_voltage3",
+ "cpr1_init_voltage4",
+ "cpr1_ring_osc1",
+ "cpr1_ring_osc2",
+ "cpr1_ring_osc3",
+ "cpr1_ring_osc4";
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000>, /* GICD */
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh
2023-01-10 17:56 ` [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio
@ 2023-01-10 18:45 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2023-01-10 18:45 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, angelogioacchino.delregno,
AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel
On 10.01.2023 18:56, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>
> Now that the CPR v3/v4/Hardened is ready, enable it on MSM8998.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> [Konrad: separate from adding cpufreq, sort nodes and use lowercase hex]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
This patch has many things wrong, please ignore..
Konrad
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 325 ++++++++++++++++++++++++++
> 1 file changed, 325 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index af29a4bfd109..84f73484441f 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -139,6 +139,9 @@ CPU0: cpu@0 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> + operating-points-v2 = <&cpu_gold_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
> L2_0: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> @@ -153,6 +156,9 @@ CPU1: cpu@1 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> + operating-points-v2 = <&cpu_gold_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
> };
>
> CPU2: cpu@2 {
> @@ -163,6 +169,9 @@ CPU2: cpu@2 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> + operating-points-v2 = <&cpu_gold_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
> };
>
> CPU3: cpu@3 {
> @@ -173,6 +182,9 @@ CPU3: cpu@3 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> + operating-points-v2 = <&cpu_gold_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
> };
>
> CPU4: cpu@100 {
> @@ -183,6 +195,9 @@ CPU4: cpu@100 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> + operating-points-v2 = <&cpu_silver_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> L2_1: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> @@ -197,6 +212,9 @@ CPU5: cpu@101 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> + operating-points-v2 = <&cpu_silver_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> };
>
> CPU6: cpu@102 {
> @@ -207,6 +225,9 @@ CPU6: cpu@102 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> + operating-points-v2 = <&cpu_silver_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> };
>
> CPU7: cpu@103 {
> @@ -217,6 +238,9 @@ CPU7: cpu@103 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> + operating-points-v2 = <&cpu_silver_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> };
>
> cpu-map {
> @@ -310,6 +334,65 @@ scm {
> };
> };
>
> + cpu_gold_opp_table: opp-table-gold {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-2208000000 {
> + opp-hz = /bits/ 64 <2208000000>;
> + required-opps = <&cprh_opp3>;
> + };
> +
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + required-opps = <&cprh_opp2>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cpu_silver_opp_table: opp-table-silver {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + required-opps = <&cprh_opp3>;
> + };
> +
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + required-opps = <&cprh_opp2>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cprh_opp_table: opp-table-cprh {
> + compatible = "operating-points-v2-qcom-level";
> +
> + cprh_opp1: opp1 {
> + opp-level = <1>;
> + qcom,opp-fuse-level = <1>;
> + };
> +
> + cprh_opp2: opp2 {
> + opp-level = <2>;
> + qcom,opp-fuse-level = <2>;
> + };
> +
> + cprh_opp3: opp3 {
> + opp-level = <3>;
> + qcom,opp-fuse-level = <2 3>;
> + };
> + };
> +
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> @@ -839,6 +922,174 @@ qfprom: qfprom@784000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> + cpr_efuse_speedbin: speedbin@133 {
> + reg = <0x133 0x8>;
> + bits = <5 3>;
> + };
> +
> + cpr_fuse_revision: cpr_fusing_rev@13e {
> + reg = <0x13e 0x1>;
> + bits = <3 3>;
> + };
> +
> + /* CPR Ring Oscillator: Power Cluster */
> + cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 {
> + reg = <0x218 0x1>;
> + bits = <0 4>;
> + };
> +
> + cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 {
> + reg = <0x218 0x1>;
> + bits = <4 4>;
> + };
> +
> + cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 {
> + reg = <0x219 0x1>;
> + bits = <0 4>;
> + };
> +
> + cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 {
> + reg = <0x219 0x1>;
> + bits = <4 4>;
> + };
> +
> + /* CPR Init Voltage: Power Cluster */
> + cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a {
> + reg = <0x21a 0x1>;
> + bits = <0 6>;
> + };
> +
> + cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a {
> + reg = <0x21a 0x1>;
> + bits = <6 6>;
> + };
> +
> + cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b {
> + reg = <0x21b 0x1>;
> + bits = <4 6>;
> + };
> +
> + cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c {
> + reg = <0x21c 0x1>;
> + bits = <2 6>;
> + };
> +
> + /* CPR Target Quotients: Power Cluster */
> + cpr_quot3_pwrcl: quot3_pwrcl@21d {
> + reg = <0x21d 0x2>;
> + bits = <6 12>;
> + };
> +
> + cpr_quot2_pwrcl: quot2_pwrcl@21f {
> + reg = <0x21f 0x2>;
> + bits = <2 11>;
> + };
> +
> + cpr_quot1_pwrcl: quot1_pwrcl@220 {
> + reg = <0x220 0x2>;
> + bits = <6 12>;
> + };
> +
> + cpr_quot0_pwrcl: quot0_pwrcl@222 {
> + reg = <0x222 0x2>;
> + bits = <2 12>;
> + };
> +
> + /* CPR Quotient Offsets: Power Cluster */
> + cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 {
> + reg = <0x226 0x1>;
> + bits = <1 7>;
> + };
> +
> + cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 {
> + reg = <0x227 0x1>;
> + bits = <0 7>;
> + };
> +
> + cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 {
> + reg = <0x227 0x1>;
> + bits = <7 6>;
> + };
> +
> + /* CPR Ring Oscillator: Performance Cluster */
> + cpr_ro_sel3_perfcl: rosel3_perfcl@229 {
> + reg = <0x229 0x1>;
> + bits = <6 4>;
> + };
> +
> + cpr_ro_sel2_perfcl: rosel2_perfcl@22a {
> + reg = <0x22a 0x1>;
> + bits = <2 4>;
> + };
> +
> + cpr_ro_sel1_perfcl: rosel1_perfcl@22a {
> + reg = <0x22a 0x1>;
> + bits = <6 4>;
> + };
> +
> + cpr_ro_sel0_perfcl: rosel0_perfcl@22b {
> + reg = <0x22b 0x1>;
> + bits = <2 4>;
> + };
> +
> + /* CPR Init Voltage: Performance Cluster */
> + cpr_init_voltage3_perfcl: ivolt3_perfcl@22b {
> + reg = <0x22b 0x1>;
> + bits = <6 6>;
> + };
> +
> + cpr_init_voltage2_perfcl: ivolt2_perfcl@22c {
> + reg = <0x22c 0x1>;
> + bits = <4 6>;
> + };
> +
> + cpr_init_voltage1_perfcl: ivolt1_perfcl@22d {
> + reg = <0x22d 0x1>;
> + bits = <2 6>;
> + };
> +
> + cpr_init_voltage0_perfcl: ivolt0_perfcl@22e {
> + reg = <0x22e 0x1>;
> + bits = <0 6>;
> + };
> +
> + /* CPR Target Quotients: Performance Cluster */
> + cpr_quot3_perfcl: quot3_perfcl@22f {
> + reg = <0x22f 0x2>;
> + bits = <4 11>;
> + };
> +
> + cpr_quot2_perfcl: quot2_perfcl@231 {
> + reg = <0x231 0x2>;
> + bits = <0 12>;
> + };
> +
> + cpr_quot1_perfcl: quot1_perfcl@232 {
> + reg = <0x232 0x2>;
> + bits = <4 12>;
> + };
> +
> + cpr_quot0_perfcl: quot0_perfcl@234 {
> + reg = <0x234 0x2>;
> + bits = <0 12>;
> + };
> +
> + /* CPR Quotient Offsets: Performance Cluster */
> + cpr_quot_offset3_perfcl: qoff3_perfcl@237 {
> + reg = <0x237 0x1>;
> + bits = <7 6>;
> + };
> +
> + cpr_quot_offset2_perfcl: qoff2_perfcl@238 {
> + reg = <0x238 0x1>;
> + bits = <6 7>;
> + };
> +
> + cpr_quot_offset1_perfcl: qoff1_perfcl@239 {
> + reg = <0x239 0x1>;
> + bits = <5 3>;
> + };
> +
> qusb2_hstx_trim: hstx-trim@23a {
> reg = <0x23a 0x1>;
> bits = <0 4>;
> @@ -2998,6 +3249,80 @@ frame@17928000 {
> };
> };
>
> + apc_cprh: power-controller@179c8000 {
> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
> + reg = <0x0179c4000 0x4000>, <0x0179c8000 0x4000>;
> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
> + clock-names = "ref";
> + operating-points-v2 = <&cprh_opp_table>;
> + #power-domain-cells = <1>;
> +
> + nvmem-cells = <&cpr_efuse_speedbin>,
> + <&cpr_fuse_revision>,
> + <&cpr_quot0_pwrcl>,
> + <&cpr_quot1_pwrcl>,
> + <&cpr_quot2_pwrcl>,
> + <&cpr_quot3_pwrcl>,
> + <&cpr_quot_offset1_pwrcl>,
> + <&cpr_quot_offset2_pwrcl>,
> + <&cpr_quot_offset3_pwrcl>,
> + <&cpr_init_voltage0_pwrcl>,
> + <&cpr_init_voltage1_pwrcl>,
> + <&cpr_init_voltage2_pwrcl>,
> + <&cpr_init_voltage3_pwrcl>,
> + <&cpr_ro_sel0_pwrcl>,
> + <&cpr_ro_sel1_pwrcl>,
> + <&cpr_ro_sel2_pwrcl>,
> + <&cpr_ro_sel3_pwrcl>,
> + <&cpr_quot0_perfcl>,
> + <&cpr_quot1_perfcl>,
> + <&cpr_quot2_perfcl>,
> + <&cpr_quot3_perfcl>,
> + <&cpr_quot_offset1_perfcl>,
> + <&cpr_quot_offset2_perfcl>,
> + <&cpr_quot_offset3_perfcl>,
> + <&cpr_init_voltage0_perfcl>,
> + <&cpr_init_voltage1_perfcl>,
> + <&cpr_init_voltage2_perfcl>,
> + <&cpr_init_voltage3_perfcl>,
> + <&cpr_ro_sel0_perfcl>,
> + <&cpr_ro_sel1_perfcl>,
> + <&cpr_ro_sel2_perfcl>,
> + <&cpr_ro_sel3_perfcl>;
> + nvmem-cell-names = "cpr_speed_bin",
> + "cpr_fuse_revision",
> + "cpr0_quotient1",
> + "cpr0_quotient2",
> + "cpr0_quotient3",
> + "cpr0_quotient4",
> + "cpr0_quotient_offset2",
> + "cpr0_quotient_offset3",
> + "cpr0_quotient_offset4",
> + "cpr0_init_voltage1",
> + "cpr0_init_voltage2",
> + "cpr0_init_voltage3",
> + "cpr0_init_voltage4",
> + "cpr0_ring_osc1",
> + "cpr0_ring_osc2",
> + "cpr0_ring_osc3",
> + "cpr0_ring_osc4",
> + "cpr1_quotient1",
> + "cpr1_quotient2",
> + "cpr1_quotient3",
> + "cpr1_quotient4",
> + "cpr1_quotient_offset2",
> + "cpr1_quotient_offset3",
> + "cpr1_quotient_offset4",
> + "cpr1_init_voltage1",
> + "cpr1_init_voltage2",
> + "cpr1_init_voltage3",
> + "cpr1_init_voltage4",
> + "cpr1_ring_osc1",
> + "cpr1_ring_osc2",
> + "cpr1_ring_osc3",
> + "cpr1_ring_osc4";
> + };
> +
> intc: interrupt-controller@17a00000 {
> compatible = "arm,gic-v3";
> reg = <0x17a00000 0x10000>, /* GICD */
^ permalink raw reply [flat|nested] 10+ messages in thread