Re: [PATCH v2 10/10] arm64: dts: sc7180: Add clock controller nodes

[Taniya Das <tdas@codeaurora.org>]

Hi Doug,

Thanks for the patch.

On 1/25/2020 4:12 AM, Douglas Anderson wrote:
> From: Taniya Das <tdas@codeaurora.org>
> 
> Add the display, video & graphics clock controller nodes supported on
> SC7180.
> 
> NOTE: the dispcc needs input clocks from various PHYs that aren't in
> the device tree yet.  For now we'll leave these stubbed out with <0>,
> which is apparently the magic way to do this.  These clocks aren't
> really "optional" and this stubbing out method is apparently the best
> way to handle it.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
> 
> Changes in v2:
> - Added includes
> - Changed various parent names to match bindings / driver
> 
>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 41 ++++++++++++++++++++++++++++
>   1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8011c5fe2a31..ee3b4bade66b 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -5,7 +5,9 @@
>    * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>    */
>   
> +#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
>   #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +#include <dt-bindings/clock/qcom,gpucc-sc7180.h>

My bad, but we are still missing the videocc header. I could send across 
the new patch.
>   #include <dt-bindings/clock/qcom,rpmh.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/phy/phy-qcom-qusb2.h>
> @@ -1039,6 +1041,18 @@ pinmux {
>   			};
>   		};
>   
> +		gpucc: clock-controller@5090000 {
> +			compatible = "qcom,sc7180-gpucc";
> +			reg = <0 0x05090000 0 0x9000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +			clock-names = "xo", "gpll0", "gpll0_div";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>   		qspi: spi@88dc000 {
>   			compatible = "qcom,qspi-v1";
>   			reg = <0 0x088dc000 0 0x600>;
> @@ -1151,6 +1165,33 @@ usb_1_dwc3: dwc3@a600000 {
>   			};
>   		};
>   
> +		videocc: clock-controller@ab00000 {
> +			compatible = "qcom,sc7180-videocc";
> +			reg = <0 0x0ab00000 0 0x10000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> +			clock-names = "xo";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		dispcc: clock-controller@af00000 {
> +			compatible = "qcom,sc7180-dispcc";
> +			reg = <0 0x0af00000 0 0x200000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
> +			clock-names = "xo", "gpll0",
> +				      "dsi_phy_pll_byte", "dsi_phy_pll_pixel",
> +				      "dp_phy_pll_link", "dp_phy_pll_vco_div";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>   		pdc: interrupt-controller@b220000 {
>   			compatible = "qcom,sc7180-pdc", "qcom,pdc";
>   			reg = <0 0x0b220000 0 0x30000>;
> 

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