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Tue, 5 Sep 2023 07:12:52 GMT Received: from [10.216.59.199] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 5 Sep 2023 00:12:43 -0700 Message-ID: Date: Tue, 5 Sep 2023 12:42:39 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH 5/5] phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY support Content-Language: en-US To: Krzysztof Kozlowski , , , , , , , , , , , CC: , , , , , References: <1693889028-6485-1-git-send-email-quic_rohiagar@quicinc.com> <1693889028-6485-6-git-send-email-quic_rohiagar@quicinc.com> From: Rohit Agarwal In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6gMUXBwzH0ZJnEaRjMa5H2DnoakGMSdI X-Proofpoint-GUID: 6gMUXBwzH0ZJnEaRjMa5H2DnoakGMSdI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-05_05,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxlogscore=751 clxscore=1015 adultscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309050063 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9/5/2023 12:23 PM, Krzysztof Kozlowski wrote: > On 05/09/2023 06:43, Rohit Agarwal wrote: >> Add support for USB3 QMP PHY found in SDX75 platform. >> >> Signed-off-by: Rohit Agarwal >> --- > > >> >> +static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { >> + .lanes = 1, >> + .offsets = &qmp_usb_offsets_v5, >> + >> + .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, >> + .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl), >> + .tx_tbl = sdx75_usb3_uniphy_tx_tbl, >> + .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl), >> + .rx_tbl = sdx75_usb3_uniphy_rx_tbl, >> + .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl), >> + .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl, >> + .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl), >> + .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl, >> + .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl), >> + .clk_list = qmp_v4_sdx55_usbphy_clk_l, >> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), >> + .reset_list = msm8996_usb3phy_reset_l, >> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), >> + .vreg_list = qmp_phy_vreg_l, >> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), >> + .regs = qmp_v5_usb3phy_regs_layout, >> + .pcs_usb_offset = 0x1000, >> + >> + .has_pwrdn_delay = true, >> + > Stray blank line > >> +}; >> + >> static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { >> .lanes = 2, >> >> @@ -1985,6 +2141,7 @@ static int qmp_usb_init(struct phy *phy) >> void __iomem *dp_com = qmp->dp_com; >> int ret; >> >> + > No need for this. This got added because I was trying to debug earlier. Sorry for this. But this should get caught by checkpatch, shouldnt it? I did run checkpatch script. Thanks, Rohit. > > Best regards, > Krzysztof >