From: Rajendra Nayak <rnayak@codeaurora.org>
To: Matthias Kaehlcke <mka@chromium.org>
Cc: viresh.kumar@linaro.org, sboyd@kernel.org,
bjorn.andersson@linaro.org, agross@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Alok Chauhan <alokc@codeaurora.org>,
Akash Asthana <akashast@codeaurora.org>,
linux-spi@vger.kernel.org
Subject: Re: [PATCH 03/21] spi: spi-geni-qcom: Use OPP API to set clk/perf state
Date: Mon, 13 Apr 2020 19:32:33 +0530 [thread overview]
Message-ID: <ef2fc62f-bc43-5689-d1a5-d1b28342b7d6@codeaurora.org> (raw)
In-Reply-To: <20200409182021.GT199755@google.com>
On 4/9/2020 11:50 PM, Matthias Kaehlcke wrote:
> Hi Rajendra,
>
> On Wed, Apr 08, 2020 at 07:16:29PM +0530, Rajendra Nayak wrote:
>> geni spi needs to express a perforamnce state requirement on CX
>> depending on the frequency of the clock rates. Use OPP table from
>> DT to register with OPP framework and use dev_pm_opp_set_rate() to
>> set the clk/perf state.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Alok Chauhan <alokc@codeaurora.org>
>> Cc: Akash Asthana <akashast@codeaurora.org>
>> Cc: linux-spi@vger.kernel.org
>> ---
>> drivers/spi/spi-geni-qcom.c | 14 +++++++++++---
>> 1 file changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
>> index c397242..ce387dc 100644
>> --- a/drivers/spi/spi-geni-qcom.c
>> +++ b/drivers/spi/spi-geni-qcom.c
>> @@ -7,6 +7,7 @@
>> #include <linux/log2.h>
>> #include <linux/module.h>
>> #include <linux/platform_device.h>
>> +#include <linux/pm_opp.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/qcom-geni-se.h>
>> #include <linux/spi/spi.h>
>> @@ -95,7 +96,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
>> {
>> unsigned long sclk_freq;
>> unsigned int actual_hz;
>> - struct geni_se *se = &mas->se;
>> int ret;
>>
>> ret = geni_se_clk_freq_match(&mas->se,
>> @@ -112,9 +112,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
>>
>> dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
>> actual_hz, sclk_freq, *clk_idx, *clk_div);
>> - ret = clk_set_rate(se->clk, sclk_freq);
>> + ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
>> if (ret)
>> - dev_err(mas->dev, "clk_set_rate failed %d\n", ret);
>> + dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
>> return ret;
>> }
>>
>> @@ -553,6 +553,7 @@ static int spi_geni_probe(struct platform_device *pdev)
>> if (!spi)
>> return -ENOMEM;
>>
>> +
>> platform_set_drvdata(pdev, spi);
>> mas = spi_master_get_devdata(spi);
>> mas->irq = irq;
>> @@ -561,6 +562,8 @@ static int spi_geni_probe(struct platform_device *pdev)
>> mas->se.wrapper = dev_get_drvdata(dev->parent);
>> mas->se.base = base;
>> mas->se.clk = clk;
>> + mas->se.opp = dev_pm_opp_set_clkname(&pdev->dev, "se");
>
> As commented on the serial patch, it seems an error check is needed
> and the OPP table saved in 'struct geni_se' is never used.
right, I explained about the OPP table in the other patch.
>
>> + dev_pm_opp_of_add_table(&pdev->dev);
>
> This function could also fail for multiple reasons, so the return value
> should be checked.
>
> From patch "[01/21] opp: Manage empty OPP tables with clk handle" it seems
> ignoring errors is intended to be able to operate when no OPP table is
> specified. But even with that you want to return in case of certain errors,
> like an invalid OPP table, out of memory or -EPROBE_DEFER.
Thats correct, my intention of not checking the errors was in cases where its
optional, and I did not want to break anything with existing DT. I will go back and
check if its indeed possible for it to return a -EPROBE_DEFER and others which
I should handle.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-04-13 14:03 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 13:46 [PATCH 00/21] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-08 13:46 ` [PATCH 01/21] opp: Manage empty OPP tables with clk handle Rajendra Nayak
2020-04-09 7:57 ` Viresh Kumar
2020-04-13 10:34 ` Rajendra Nayak
2020-04-13 10:42 ` Viresh Kumar
2020-04-14 6:57 ` Viresh Kumar
2020-04-08 13:46 ` [PATCH 02/21] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-09 17:45 ` Matthias Kaehlcke
2020-04-10 8:36 ` Jun Nie
2020-04-13 14:22 ` Rajendra Nayak
2020-04-14 5:26 ` Jun Nie
2020-04-13 13:58 ` Rajendra Nayak
2020-04-10 6:56 ` Akash Asthana
2020-04-10 12:52 ` Akash Asthana
2020-04-13 14:13 ` Rajendra Nayak
2020-04-08 13:46 ` [PATCH 03/21] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-09 18:20 ` Matthias Kaehlcke
2020-04-13 14:02 ` Rajendra Nayak [this message]
2020-04-08 13:46 ` [PATCH 04/21] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-08 13:46 ` [PATCH 05/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 06/21] scsi: ufs: Add support to manage multiple power domains in ufshcd-pltfrm Rajendra Nayak
2020-04-08 13:46 ` [PATCH 07/21] scsi: ufs: Add support for specifying OPP tables in DT Rajendra Nayak
2020-04-08 13:46 ` [PATCH 08/21] arm64: dts: sdm845: Add ufs opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 09/21] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 10/21] drm/msm: dsi: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 11/21] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 12/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 13/21] mmc: sdhci-msm: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-15 13:52 ` Ulf Hansson
2020-04-15 16:43 ` Rajendra Nayak
2020-04-16 3:39 ` Viresh Kumar
2020-04-16 8:21 ` Ulf Hansson
2020-04-16 8:23 ` Ulf Hansson
2020-04-08 13:46 ` [PATCH 14/21] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 15/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 16/21] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-08 13:46 ` [PATCH 17/21] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-08 13:46 ` [PATCH 18/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 19/21] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 20/21] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 21/21] arm64: dts: sc7180: " Rajendra Nayak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ef2fc62f-bc43-5689-d1a5-d1b28342b7d6@codeaurora.org \
--to=rnayak@codeaurora.org \
--cc=agross@kernel.org \
--cc=akashast@codeaurora.org \
--cc=alokc@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=mka@chromium.org \
--cc=sboyd@kernel.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).