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Wed, 13 Nov 2024 03:15:45 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AD3FiTU000592 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 03:15:44 GMT Received: from [10.239.29.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 12 Nov 2024 19:15:38 -0800 Message-ID: Date: Wed, 13 Nov 2024 11:15:35 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 5/5] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 To: Johan Hovold CC: , , , , , , , , , , , , , , , , , , , , , , , References: <20241101030902.579789-1-quic_qianyu@quicinc.com> <20241101030902.579789-6-quic_qianyu@quicinc.com> Content-Language: en-US From: Qiang Yu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GcnROkpzv1BlU-MSswyL8At-npoyDzuB X-Proofpoint-ORIG-GUID: GcnROkpzv1BlU-MSswyL8At-npoyDzuB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=812 adultscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130027 On 11/13/2024 1:29 AM, Johan Hovold wrote: > On Mon, Nov 11, 2024 at 11:44:17AM +0800, Qiang Yu wrote: >> On 11/5/2024 1:28 PM, Qiang Yu wrote: >>> On 11/4/2024 10:35 PM, Johan Hovold wrote: >>>> On Thu, Oct 31, 2024 at 08:09:02PM -0700, Qiang Yu wrote: >>>>> +            ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 >>>>> 0x100000>, >>>>> +                 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 >>>>> 0x3d00000>, >>>> Can you double check the size here so that it is indeed correct and not >>>> just copied from the other nodes which initially got it wrong: >>>> >>>>     https://lore.kernel.org/lkml/20240710-topic-barman-v1-1-5f63fca8d0fc@linaro.org/ >> BTW, regions of PCIe6a, PCIe4, PCIe5 are 64MB, 32MB, 32MB, respectively. >> Why range size is set to 0x1d00000 for PCIe6a, any issue is reported on >> PCIe6a? > Thanks for checking. It seems the patch linked to above was broken for > PCIe6a then. > > We did see PCIe5 probe breaking due to the overlap with PCIe4 but the > patch predates PCIe5 support being posted and merged so it was probably > just based on inspection. > > Could you send a fix for PCIe6a? Sure, will send the fix. Thanks, Qiang Yu > > Johan