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Tue, 03 Dec 2024 09:06:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B396i7u022822 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 09:06:44 GMT Received: from [10.216.45.237] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 3 Dec 2024 01:06:38 -0800 Message-ID: Date: Tue, 3 Dec 2024 14:36:35 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615 To: Dmitry Baryshkov , Manivannan Sadhasivam CC: Krzysztof Kozlowski , , "Bjorn Helgaas" , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , Jingoo Han , Bartosz Golaszewski , , , , , References: <20241112-qps615_pwr-v3-0-29a1e98aa2b0@quicinc.com> <20241112-qps615_pwr-v3-1-29a1e98aa2b0@quicinc.com> <42425b92-6e0d-a77b-8733-e50614bcb3a8@quicinc.com> <20241128132432.fxvmjeluagignbph@thinkpad> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cAVDdmet4GDfh2W6IcOqJKLzWQblj0EB X-Proofpoint-ORIG-GUID: cAVDdmet4GDfh2W6IcOqJKLzWQblj0EB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 mlxlogscore=931 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030078 On 11/28/2024 7:38 PM, Dmitry Baryshkov wrote: > On Thu, Nov 28, 2024 at 06:54:32PM +0530, Manivannan Sadhasivam wrote: >> On Tue, Nov 26, 2024 at 07:58:16AM +0100, Krzysztof Kozlowski wrote: >>> On 26/11/2024 07:50, Krishna Chaitanya Chundru wrote: >>>> >>>> >>>> On 11/25/2024 1:10 PM, Krzysztof Kozlowski wrote: >>>>> On 24/11/2024 02:41, Krishna Chaitanya Chundru wrote: >>>>>>> ... >>>>>>> >>>>>>>> + qps615,axi-clk-freq-hz: >>>>>>> >>>>>>> That's a downstream code you send us. >>>>>>> >>>>>>> Anyway, why assigned clock rates do not work for you? You are >>>>>>> re-implementing legacy property now under different name :/ >>>>>>> >>>>>>> The assigned clock rates comes in to the picture when we are >>>>>>> using clock >>>>>> framework to control the clocks. For this switch there are no >>>>>> clocks needs to be control, the moment we power on the switch >>>>>> clocks are enabled by default. This switch provides a mechanism to >>>>>> control the frequency using i2c. And switch supports only two >>>>>> frequencies i.e >>>>> >>>>> >>>>> frequency of what, since there are no clocks? >>>>> >>>> The axi clock frequency internal to the switch, host can't control >>>> the enablement of the clocks it can control only the frequency. >>>> >>>> we already had a discussion on this on v2[1], and we taught you agreed >>>> on this property. >>>> >>>> [1] >>>> https://lore.kernel.org/netdev/d1af1eac-f9bd-7a8e-586b-5c2a76445145@codeaurora.org/T/#m3d5864c758f2e05fa15ba522aad6a37e3417bd9f >>>> >>> >>> This points something else. I diged v2 and found many unanswered >>> questions and unfinished discussion: >>> >> >> The conversation is here: >> https://lore.kernel.org/linux-arm-msm/20240823094028.7xul4eoiexey5xjm@thinkpad/ >> >> But there was no explicit agreement on the usage of 'qps615,axi-clk-freq-hz'. >> >> If describing the PCI device's internal clock frequency is not applicable, then >> I'd recommend to change the clock rate in the driver itself based on the number >> of DSPs enabled (or based on other configuration). > > Sounds like the best approach. Otherwise it's not obvious, what is the > criteria for selecting this or that clock value. > I will remove this property in next patch and driver code to set this frequency in the next patch, we will try to come up with some logic later. - Krishna chaitanya. >> >> - Mani >> >> -- >> மணிவண்ணன் சதாசிவம் >