From: Lucas Stach <l.stach@pengutronix.de>
To: Richard Zhu <hongxing.zhu@nxp.com>,
p.zabel@pengutronix.de, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org,
vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de,
richard.leitner@linux.dev
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v6 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding
Date: Fri, 02 Sep 2022 10:32:28 +0200 [thread overview]
Message-ID: <ef4b87af234375994b8efd34c6ac0e64a4a0400d.camel@pengutronix.de> (raw)
In-Reply-To: <1662004960-14071-2-git-send-email-hongxing.zhu@nxp.com>
Am Donnerstag, dem 01.09.2022 um 12:02 +0800 schrieb Richard Zhu:
> Add i.MX8MP PCIe PHY binding.
> On iMX8MM, the initialized default value of PERST bit(BIT3) of
> SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
>
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So add one more PERST explicitly for i.MX8MP PCIe PHY.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> index b6421eedece3..692783c7fd69 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> @@ -16,6 +16,7 @@ properties:
> compatible:
> enum:
> - fsl,imx8mm-pcie-phy
> + - fsl,imx8mp-pcie-phy
>
> reg:
> maxItems: 1
> @@ -28,11 +29,16 @@ properties:
> - const: ref
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> reset-names:
> - items:
> - - const: pciephy
> + oneOf:
> + - items: # for iMX8MM
> + - const: pciephy
> + - items: # for IMX8MP
> + - const: pciephy
> + - const: perst
>
> fsl,refclk-pad-mode:
> description: |
> @@ -60,6 +66,10 @@ properties:
> description: A boolean property indicating the CLKREQ# signal is
> not supported in the board design (optional)
>
> + power-domains:
> + description: PCIe PHY power domain (optional).
> + maxItems: 1
> +
> required:
> - "#phy-cells"
> - compatible
next prev parent reply other threads:[~2022-09-02 8:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 4:02 [PATCH v6 0/7] Add the iMX8MP PCIe support Richard Zhu
2022-09-01 4:02 ` [PATCH v6 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding Richard Zhu
2022-09-02 8:32 ` Lucas Stach [this message]
2022-09-01 4:02 ` [PATCH v6 2/7] arm64: dts: imx8mp: Add iMX8MP PCIe support Richard Zhu
2022-09-02 8:42 ` Lucas Stach
2022-09-01 4:02 ` [PATCH v6 3/7] arm64: dts: imx8mp-evk: Add " Richard Zhu
2022-09-02 8:47 ` Lucas Stach
2022-09-01 4:02 ` [PATCH v6 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support Richard Zhu
2022-09-01 4:02 ` [PATCH v6 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets Richard Zhu
2022-09-01 4:02 ` [PATCH v6 6/7] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
2022-09-02 8:38 ` Lucas Stach
2022-09-02 9:04 ` Hongxing Zhu
2022-09-01 4:02 ` [PATCH v6 7/7] PCI: imx6: Add i.MX8MP PCIe support Richard Zhu
2022-09-02 8:41 ` Lucas Stach
2022-09-02 9:02 ` Hongxing Zhu
2022-09-09 9:39 ` Lorenzo Pieralisi
2022-09-09 9:48 ` Lucas Stach
-- strict thread matches above, loose matches on Subject: below --
2022-09-02 8:55 [PATCH v7 0/7] Add the iMX8MP " Richard Zhu
2022-09-02 8:55 ` [PATCH v6 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding Richard Zhu
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