From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF6ED2C21F7; Mon, 20 Oct 2025 13:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760968060; cv=none; b=nSg8Lijp8sLeEjWxEmaCyScYtv0gvEeHIx1OOc/0R/jQEdJK8anyVgSk9K+V646jMQWzxsCnHoNdlAgfIa05PRDbKlGADH2BsK1cx8L7ANQO4cVHjA+a8a0Fl/7N/hOkipfgi7gDXWqVQJz0fgZ5mtbarxjCpudqtSyVzEEhsL8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760968060; c=relaxed/simple; bh=7xW28T3apWZwrY81wJCRu3IdXgTZGX/t1f963bLJQoo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=eKYxnZVpuEFDxzFKkvmp6pHCSAdVQIkBCy8zmz/ZFhtqwhxLtr2ED3/u8ujrv6Eh148GgT4AcDmqF9y7FLO/v0ZNVZn291bWGd7NLlxK2+XjxtovGntzaN+eON7+WN1EdaqR1o3UU0Xw3Z8Fh8CMUKsUKnKMmQOmmBxcrOBJDoU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FCBA16A3; Mon, 20 Oct 2025 06:47:30 -0700 (PDT) Received: from [10.57.36.117] (unknown [10.57.36.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF81F3F66E; Mon, 20 Oct 2025 06:47:32 -0700 (PDT) Message-ID: Date: Mon, 20 Oct 2025 14:47:30 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 4/5] drm/panthor: Use existing OPP table if present To: Nicolas Frattaroli , AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org References: <20251017-mt8196-gpufreq-v8-0-98fc1cc566a1@collabora.com> <20251017-mt8196-gpufreq-v8-4-98fc1cc566a1@collabora.com> From: Steven Price Content-Language: en-GB In-Reply-To: <20251017-mt8196-gpufreq-v8-4-98fc1cc566a1@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/10/2025 16:31, Nicolas Frattaroli wrote: > On SoCs where the GPU's power-domain is in charge of setting performance > levels, the OPP table of the GPU node will have already been populated > during said power-domain's attach_dev operation. > > To avoid initialising an OPP table twice, only set the OPP regulator and > the OPPs from DT if there's no OPP table present. > > Reviewed-by: Chia-I Wu > Reviewed-by: AngeloGioacchino Del Regno > Signed-off-by: Nicolas Frattaroli Reviewed-by: Steven Price > --- > drivers/gpu/drm/panthor/panthor_devfreq.c | 32 ++++++++++++++++++++++--------- > 1 file changed, 23 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/panthor/panthor_devfreq.c > index a6dca599f0a5..ec63e27f4883 100644 > --- a/drivers/gpu/drm/panthor/panthor_devfreq.c > +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c > @@ -141,6 +141,7 @@ int panthor_devfreq_init(struct panthor_device *ptdev) > struct thermal_cooling_device *cooling; > struct device *dev = ptdev->base.dev; > struct panthor_devfreq *pdevfreq; > + struct opp_table *table; > struct dev_pm_opp *opp; > unsigned long cur_freq; > unsigned long freq = ULONG_MAX; > @@ -152,17 +153,30 @@ int panthor_devfreq_init(struct panthor_device *ptdev) > > ptdev->devfreq = pdevfreq; > > - ret = devm_pm_opp_set_regulators(dev, reg_names); > - if (ret && ret != -ENODEV) { > - if (ret != -EPROBE_DEFER) > - DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n"); > - return ret; > + /* > + * The power domain associated with the GPU may have already added an > + * OPP table, complete with OPPs, as part of the platform bus > + * initialization. If this is the case, the power domain is in charge of > + * also controlling the performance, with a set_performance callback. > + * Only add a new OPP table from DT if there isn't such a table present > + * already. > + */ > + table = dev_pm_opp_get_opp_table(dev); > + if (IS_ERR_OR_NULL(table)) { > + ret = devm_pm_opp_set_regulators(dev, reg_names); > + if (ret && ret != -ENODEV) { > + if (ret != -EPROBE_DEFER) > + DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n"); > + return ret; > + } > + > + ret = devm_pm_opp_of_add_table(dev); > + if (ret) > + return ret; > + } else { > + dev_pm_opp_put_opp_table(table); > } > > - ret = devm_pm_opp_of_add_table(dev); > - if (ret) > - return ret; > - > spin_lock_init(&pdevfreq->lock); > > panthor_devfreq_reset(pdevfreq); >