Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Robert Marko <robimarko@gmail.com>]

On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
>> the CPU frequency at optimal range.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>>   1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..05843517312c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> c is before r.
>
>>   
>>   / {
>>   	interrupt-parent = <&intc>;
>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>>   			reg = <0x0>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		CPU1: cpu@1 {
>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>>   			reg = <0x1>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		L2_0: l2-cache {
>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>>   		};
>>   	};
>>   
>> +	cpu_opp_table: opp-table-cpu {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-1008000000 {
>> +			opp-hz = /bits/ 64 <1008000000>;
>> +			opp-microvolt = <1100000>;
>> +			clock-latency-ns = <200000>;
> And the rest of OPPs?
Hi Krzysztof,
IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
by default from the bootloader so there is only one OPP.

I am glad to see more SoC-s gaining CPUFreq support.

Regards,
Robert
>
>> +		};
>> +	};
>> +
>>   	firmware {
>>   		scm {
>>   			compatible = "qcom,scm-ipq5018", "qcom,scm";
>> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
>>   			};
>>   		};
>>   
>> +		a53pll: clock@b116000 {
>> +			compatible = "qcom,ipq5018-a53pll";
>> +			reg = <0x0b116000 0x40>;
>> +			#clock-cells = <0>;
>> +			clocks = <&xo_board_clk>;
>> +			clock-names = "xo";
>> +		};
>> +
>> +		apcs_glb: mailbox@b111000 {
> 0xb111000 looks lower than 0x116000.
>
>> +			compatible = "qcom,ipq5018-apcs-apps-global",
>> +				     "qcom,ipq6018-apcs-apps-global";
>> +			reg = <0x0b111000 0x1000>;
> Best regards,
> Krzysztof
>
>
>