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Thu, 11 Aug 2022 01:50:06 -0700 (PDT) Received: from [192.168.1.39] ([83.146.140.105]) by smtp.gmail.com with ESMTPSA id d22-20020a193856000000b0048b0c8fb31asm628821lfj.159.2022.08.11.01.50.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Aug 2022 01:50:06 -0700 (PDT) Message-ID: Date: Thu, 11 Aug 2022 11:50:05 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v3 1/4] dt-bindings: clock: mediatek: add bindings for MT8365 SoC Content-Language: en-US To: Markus Schneider-Pargmann , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Fabien Parent , AngeloGioacchino Del Regno Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent References: <20220811084433.2598575-1-msp@baylibre.com> <20220811084433.2598575-2-msp@baylibre.com> From: Krzysztof Kozlowski In-Reply-To: <20220811084433.2598575-2-msp@baylibre.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/08/2022 11:44, Markus Schneider-Pargmann wrote: > From: Fabien Parent > > Add the clock bindings for the MediaTek MT8365 SoC. > > Signed-off-by: Fabien Parent > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Markus Schneider-Pargmann > --- > .../bindings/clock/mediatek,mt8365-clock.yaml | 42 ++ > .../clock/mediatek,mt8365-sys-clock.yaml | 47 +++ > .../dt-bindings/clock/mediatek,mt8365-clk.h | 374 ++++++++++++++++++ > 3 files changed, 463 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml > create mode 100644 include/dt-bindings/clock/mediatek,mt8365-clk.h > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml > new file mode 100644 > index 000000000000..31cd248e772b > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" No quotes needed in both lines. > + > +title: MediaTek Functional Clock Controller for MT8365 > + > +maintainers: > + - Fabien Parent Are you sure this is correct and working email? Let's try not to add non-existing emails to Git maintainers. It's a bit of pain to fix it later. :/ > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8365-apu > + - mediatek,mt8365-imgsys > + - mediatek,mt8365-mfgcfg > + - mediatek,mt8365-vdecsys > + - mediatek,mt8365-vencsys > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + apu: clock-controller@19020000 { > + compatible = "mediatek,mt8365-apu", "syscon"; > + reg = <0x19020000 0x1000>; > + #clock-cells = <1>; > + }; > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml > new file mode 100644 > index 000000000000..4292a2fd1489 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" No quotes. > + > +title: MediaTek System Clock Controller for MT8365 > + > +maintainers: > + - Fabien Parent Ekh... > + > +description: > + The apmixedsys module provides most of PLLs which generated from SoC 26m. > + The topckgen provides dividers and muxes which provides the clock source to other IP blocks. > + The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8365-topckgen > + - mediatek,mt8365-infracfg > + - mediatek,mt8365-apmixedsys > + - mediatek,mt8365-pericfg > + - mediatek,mt8365-mcucfg > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt8365-topckgen", "syscon"; > + reg = <0x10000000 0x1000>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h > new file mode 100644 > index 000000000000..aa8a0366caae > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h > @@ -0,0 +1,374 @@ > +/* SPDX-License-Identifier: GPL-2.0 Can you dual-license it? > + * > + * Copyright (c) 2022 MediaTek Inc. Best regards, Krzysztof