* [PATCH 1/2] mmc: cqe: Add CQE DT support for cadence controller
2026-04-07 11:18 [PATCH 0/2] CQE support for cadence eMMC host controller rohan1sj via B4 Relay
@ 2026-04-07 11:18 ` rohan1sj via B4 Relay
2026-04-07 11:30 ` Krzysztof Kozlowski
2026-04-07 11:18 ` [PATCH 2/2] mmc: cqe: Add CQE support for cadence mmc driver rohan1sj via B4 Relay
1 sibling, 1 reply; 5+ messages in thread
From: rohan1sj via B4 Relay @ 2026-04-07 11:18 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Masahiro Yamada, Adrian Hunter
Cc: linux-mmc, devicetree, linux-kernel, Milind Parab,
Swapnil Jakhade, Manikandan Pillai, rohan1sj
From: rohan1sj <rohan1sj@cadence.com>
Add DT config required to support CQE as present in
cadence eMMC host controller
Signed-off-by: rohan1sj <rohan1sj@cadence.com>
---
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 32 +++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index ac75d694611a..c0d8aefe20c2 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -24,6 +24,10 @@ properties:
minItems: 1
maxItems: 2
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
interrupts:
maxItems: 1
@@ -139,7 +143,19 @@ allOf:
else:
properties:
reg:
- maxItems: 1
+ oneOf:
+ - items:
+ - description: Host controller registers
+ - items:
+ - description: Host controller registers
+ - description: CQE (Command Queue Engine) registers
+ reg-names:
+ oneOf:
+ - items:
+ - const: sdhci
+ - items:
+ - const: sdhci
+ - const: cqhci
unevaluatedProperties: false
@@ -156,3 +172,17 @@ examples:
mmc-hs400-1_8v;
cdns,phy-dll-delay-sdclk = <0>;
};
+
+ - |
+ emmc_cqe: mmc@5b000000 {
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
+ reg = <0x5b000000 0x400>, <0x5b000400 0x060>;
+ reg-names = "sdhci", "cqhci";
+ interrupts = <0 79 4>;
+ clocks = <&clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cdns,phy-dll-delay-sdclk = <0>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] mmc: cqe: Add CQE support for cadence mmc driver
2026-04-07 11:18 [PATCH 0/2] CQE support for cadence eMMC host controller rohan1sj via B4 Relay
2026-04-07 11:18 ` [PATCH 1/2] mmc: cqe: Add CQE DT support for cadence controller rohan1sj via B4 Relay
@ 2026-04-07 11:18 ` rohan1sj via B4 Relay
2026-04-07 11:30 ` Krzysztof Kozlowski
1 sibling, 1 reply; 5+ messages in thread
From: rohan1sj via B4 Relay @ 2026-04-07 11:18 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Masahiro Yamada, Adrian Hunter
Cc: linux-mmc, devicetree, linux-kernel, Milind Parab,
Swapnil Jakhade, Manikandan Pillai, rohan1sj
From: rohan1sj <rohan1sj@cadence.com>
Add Command Queuing Engine (CQE) support for cadence driver
Signed-off-by: rohan1sj <rohan1sj@cadence.com>
---
drivers/mmc/host/sdhci-cadence.c | 118 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 115 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 435603c8c00b..14b12272dae9 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -15,6 +15,8 @@
#include <linux/reset.h>
#include "sdhci-pltfm.h"
+#include "sdhci-cqhci.h"
+#include "cqhci.h"
/* HRS - Host Register Set (specific to Cadence) */
#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
@@ -36,6 +38,10 @@
#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
+/* Host capabilities not covered by the standard capability registers (SRS16-SRS18) */
+#define SDHCI_CDNS_HRS30 0x78 /* Host capabilities */
+#define SDHCI_CDNS_HRS30_CQE_SUPPORTED BIT(0)
+
/* Read block gap */
#define SDHCI_CDNS_HRS37 0x94 /* interface mode select */
#define SDHCI_CDNS_HRS37_MODE_DS 0x0
@@ -88,6 +94,7 @@ struct sdhci_cdns_priv {
void __iomem *ctl_addr; /* write control */
spinlock_t wrlock; /* write lock */
bool enhanced_strobe;
+ bool cqe_support; /* Command Queuing Engine support */
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
struct reset_control *rst_hw;
unsigned int nr_phy_params;
@@ -385,6 +392,73 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
sdhci_set_uhs_signaling(host, timing);
}
+static u32 sdhci_cdns_cqhci_irq(struct sdhci_host *host, u32 intmask)
+{
+ int cmd_err = 0;
+ int data_err = 0;
+
+ /* return original intmask to be handled by other handlers if it's not a CQE interrupt */
+ if (!sdhci_cqe_irq(host, intmask, &cmd_err, &data_err))
+ return intmask;
+
+ cqhci_irq(host->mmc, intmask, cmd_err, data_err);
+
+ return 0;
+}
+
+static const struct cqhci_host_ops sdhci_cdns_cqhci_ops = {
+ .enable = sdhci_cqe_enable,
+ .disable = sdhci_cqe_disable,
+};
+
+static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_device *pdev)
+{
+ struct cqhci_host *cq_host;
+ bool dma64;
+ int ret;
+
+ /* setup SDHCI host first */
+ ret = sdhci_setup_host(host);
+
+ if (ret)
+ return ret;
+
+ /* Init CQE */
+ cq_host = cqhci_pltfm_init(pdev);
+ if (IS_ERR(cq_host)) {
+ ret = PTR_ERR(cq_host);
+ goto cleanup;
+ }
+
+ dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
+ if (dma64)
+ cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+
+ cq_host->ops = &sdhci_cdns_cqhci_ops;
+
+ host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
+
+ /* Finally initialize CQHCI */
+ ret = cqhci_init(cq_host, host->mmc, dma64);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc), "Failed to initialize CQHCI: %d\n", ret);
+ goto cleanup;
+ }
+
+ /* add host to MMC subsystem */
+ ret = __sdhci_add_host(host);
+ if (ret)
+ goto cleanup;
+
+ dev_info(mmc_dev(host->mmc), "CQE init: success\n");
+ return 0;
+
+cleanup:
+ dev_err(mmc_dev(host->mmc), "CQE init: failed for %s\n", mmc_hostname(host->mmc));
+ sdhci_cleanup_host(host);
+ return ret;
+}
+
/* Elba control register bits [6:3] are byte-lane enables */
#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3)
@@ -474,9 +548,10 @@ static const struct sdhci_ops sdhci_cdns_ops = {
.set_clock = sdhci_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
.set_bus_width = sdhci_set_bus_width,
- .reset = sdhci_reset,
+ .reset = sdhci_and_cqhci_reset,
.platform_execute_tuning = sdhci_cdns_execute_tuning,
.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
+ .irq = sdhci_cdns_cqhci_irq,
};
static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
@@ -553,6 +628,8 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
int ret;
struct device *dev = &pdev->dev;
static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
+ bool cqe_enabled;
+ u32 host_caps;
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
@@ -608,7 +685,35 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;
}
- return sdhci_add_host(host);
+ host_caps = readl(priv->hrs_addr + SDHCI_CDNS_HRS30);
+ cqe_enabled = host_caps & SDHCI_CDNS_HRS30_CQE_SUPPORTED;
+
+ if (cqe_enabled) {
+ priv->cqe_support = true;
+ ret = sdhci_cdns_cqe_add_host(host, pdev);
+ } else {
+ ret = sdhci_add_host(host);
+ }
+
+ return ret;
+}
+
+static int sdhci_cdns_suspend(struct device *dev)
+{
+ struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+
+ if (priv->cqe_support) {
+ ret = cqhci_suspend(host->mmc);
+ if (ret)
+ return ret;
+ }
+
+ ret = sdhci_pltfm_suspend(dev);
+
+ return ret;
}
static int sdhci_cdns_resume(struct device *dev)
@@ -630,6 +735,13 @@ static int sdhci_cdns_resume(struct device *dev)
if (ret)
goto disable_clk;
+ /* Resume CQE if enabled */
+ if (priv->cqe_support) {
+ ret = cqhci_resume(host->mmc);
+ if (ret)
+ goto disable_clk;
+ }
+
return 0;
disable_clk:
@@ -638,7 +750,7 @@ static int sdhci_cdns_resume(struct device *dev)
return ret;
}
-static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_pltfm_suspend, sdhci_cdns_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_cdns_suspend, sdhci_cdns_resume);
static const struct of_device_id sdhci_cdns_match[] = {
{
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread