[PATCH 0/4] Add Airoha EN7581 PCIE support

[PATCH 0/4] Add Airoha EN7581 PCIE support

[Lorenzo Bianconi]

Introduce support for EN7581 SoC to mediatek-gen3 pcie driver

Lorenzo Bianconi (4):
  dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581
  PCI: mediatek-gen3: Add mtk_pcie_soc data structure
  PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines
  PCI: mediatek-gen3: Add Airoha EN7581 support

 .../bindings/pci/mediatek-pcie-gen3.yaml      |  25 ++-
 drivers/pci/controller/Kconfig                |   2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c   | 155 ++++++++++++++++--
 3 files changed, 161 insertions(+), 21 deletions(-)

-- 
2.45.2

[PATCH 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Lorenzo Bianconi]

Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 25 +++++++++++++++----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 76d742051f73..0f35cf49de63 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -53,6 +53,7 @@ properties:
               - mediatek,mt8195-pcie
           - const: mediatek,mt8192-pcie
       - const: mediatek,mt8192-pcie
+      - const: airoha,en7581-pcie
 
   reg:
     maxItems: 1
@@ -76,20 +77,20 @@ properties:
 
   resets:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   reset-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     items:
-      enum: [ phy, mac ]
+      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
 
   clocks:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   clock-names:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   assigned-clocks:
@@ -186,6 +187,20 @@ allOf:
             - const: tl_26m
             - const: peri_26m
             - const: top_133m
+  - if:
+      properties:
+        compatible:
+          const: airoha,en7581-pcie
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: sys_ck
+        reset-names:
+          items:
+            - const: phy-lane0
+            - const: phy-lane1
+            - const: phy-lane2
 
 unevaluatedProperties: false
 
-- 
2.45.2

Re: [PATCH 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2174 bytes --]

On Fri, Jun 21, 2024 at 04:48:47PM +0200, Lorenzo Bianconi wrote:
> Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  .../bindings/pci/mediatek-pcie-gen3.yaml      | 25 +++++++++++++++----
>  1 file changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index 76d742051f73..0f35cf49de63 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -53,6 +53,7 @@ properties:
>                - mediatek,mt8195-pcie
>            - const: mediatek,mt8192-pcie
>        - const: mediatek,mt8192-pcie
> +      - const: airoha,en7581-pcie
>  
>    reg:
>      maxItems: 1
> @@ -76,20 +77,20 @@ properties:
>  
>    resets:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>  
>    reset-names:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      items:
> -      enum: [ phy, mac ]
> +      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
>  
>    clocks:
> -    minItems: 4
> +    minItems: 1
>      maxItems: 6
>  
>    clock-names:
> -    minItems: 4
> +    minItems: 1

You've now relaxed the clock requirements for all devices,
and permitted an extra reset on the existing platforms. You'll need to
add some per-device min/maxItems constraints to solve that.

Thanks,
Conor.


>      maxItems: 6
>  
>    assigned-clocks:
> @@ -186,6 +187,20 @@ allOf:
>              - const: tl_26m
>              - const: peri_26m
>              - const: top_133m
> +  - if:
> +      properties:
> +        compatible:
> +          const: airoha,en7581-pcie
> +    then:
> +      properties:
> +        clock-names:
> +          items:
> +            - const: sys_ck
> +        reset-names:
> +          items:
> +            - const: phy-lane0
> +            - const: phy-lane1
> +            - const: phy-lane2
>  
>  unevaluatedProperties: false
>  
> -- 
> 2.45.2
> 
> 

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Re: [PATCH 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 2390 bytes --]

> On Fri, Jun 21, 2024 at 04:48:47PM +0200, Lorenzo Bianconi wrote:
> > Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml      | 25 +++++++++++++++----
> >  1 file changed, 20 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > index 76d742051f73..0f35cf49de63 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -53,6 +53,7 @@ properties:
> >                - mediatek,mt8195-pcie
> >            - const: mediatek,mt8192-pcie
> >        - const: mediatek,mt8192-pcie
> > +      - const: airoha,en7581-pcie
> >  
> >    reg:
> >      maxItems: 1
> > @@ -76,20 +77,20 @@ properties:
> >  
> >    resets:
> >      minItems: 1
> > -    maxItems: 2
> > +    maxItems: 3
> >  
> >    reset-names:
> >      minItems: 1
> > -    maxItems: 2
> > +    maxItems: 3
> >      items:
> > -      enum: [ phy, mac ]
> > +      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
> >  
> >    clocks:
> > -    minItems: 4
> > +    minItems: 1
> >      maxItems: 6
> >  
> >    clock-names:
> > -    minItems: 4
> > +    minItems: 1
> 
> You've now relaxed the clock requirements for all devices,
> and permitted an extra reset on the existing platforms. You'll need to
> add some per-device min/maxItems constraints to solve that.

ack, I will fix it in v2.

Regards,
Lorenzo

> 
> Thanks,
> Conor.
> 
> 
> >      maxItems: 6
> >  
> >    assigned-clocks:
> > @@ -186,6 +187,20 @@ allOf:
> >              - const: tl_26m
> >              - const: peri_26m
> >              - const: top_133m
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          const: airoha,en7581-pcie
> > +    then:
> > +      properties:
> > +        clock-names:
> > +          items:
> > +            - const: sys_ck
> > +        reset-names:
> > +          items:
> > +            - const: phy-lane0
> > +            - const: phy-lane1
> > +            - const: phy-lane2
> >  
> >  unevaluatedProperties: false
> >  
> > -- 
> > 2.45.2
> > 
> > 



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[PATCH 2/4] PCI: mediatek-gen3: Add mtk_pcie_soc data structure

[Lorenzo Bianconi]

Introduce mtk_pcie_soc data structure in order to define multiple
callbacks for each supported SoC. This is a preliminary patch to
introduce EN7581 pcie support.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 975b3024fb08..4859bd875bc4 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -100,6 +100,16 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
+struct mtk_gen3_pcie;
+
+/**
+ * struct mtk_pcie_soc - differentiate between host generations
+ * @power_up: pcie power_up callback
+ */
+struct mtk_pcie_soc {
+	int (*power_up)(struct mtk_gen3_pcie *pcie);
+};
+
 /**
  * struct mtk_msi_set - MSI information for each set
  * @base: IO mapped register base
@@ -131,6 +141,7 @@ struct mtk_msi_set {
  * @msi_sets: MSI sets information
  * @lock: lock protecting IRQ bit map
  * @msi_irq_in_use: bit map for assigned MSI IRQ
+ * @soc: pointer to SoC-dependent operations
  */
 struct mtk_gen3_pcie {
 	struct device *dev;
@@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
 	struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
 	struct mutex lock;
 	DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
+
+	const struct mtk_pcie_soc *soc;
 };
 
 /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
@@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	usleep_range(10, 20);
 
 	/* Don't touch the hardware registers before power up */
-	err = mtk_pcie_power_up(pcie);
+	err = pcie->soc->power_up(pcie);
 	if (err)
 		return err;
 
@@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
 	pcie = pci_host_bridge_priv(host);
 
 	pcie->dev = dev;
+	pcie->soc = of_device_get_match_data(dev);
 	platform_set_drvdata(pdev, pcie);
 
 	err = mtk_pcie_setup(pcie);
@@ -1054,7 +1068,7 @@ static int mtk_pcie_resume_noirq(struct device *dev)
 	struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
 	int err;
 
-	err = mtk_pcie_power_up(pcie);
+	err = pcie->soc->power_up(pcie);
 	if (err)
 		return err;
 
@@ -1074,8 +1088,12 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
 				  mtk_pcie_resume_noirq)
 };
 
+static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
+	.power_up = mtk_pcie_power_up,
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
-	{ .compatible = "mediatek,mt8192-pcie" },
+	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
-- 
2.45.2

Re: [PATCH 2/4] PCI: mediatek-gen3: Add mtk_pcie_soc data structure

[AngeloGioacchino Del Regno]

Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> Introduce mtk_pcie_soc data structure in order to define multiple
> callbacks for each supported SoC. This is a preliminary patch to
> introduce EN7581 pcie support.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
>   1 file changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 975b3024fb08..4859bd875bc4 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -100,6 +100,16 @@
>   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>   
> +struct mtk_gen3_pcie;
> +
> +/**
> + * struct mtk_pcie_soc - differentiate between host generations

mtk_gen3_pcie_pdata ?

> + * @power_up: pcie power_up callback
> + */
> +struct mtk_pcie_soc {
> +	int (*power_up)(struct mtk_gen3_pcie *pcie);
> +};
> +
>   /**
>    * struct mtk_msi_set - MSI information for each set
>    * @base: IO mapped register base
> @@ -131,6 +141,7 @@ struct mtk_msi_set {
>    * @msi_sets: MSI sets information
>    * @lock: lock protecting IRQ bit map
>    * @msi_irq_in_use: bit map for assigned MSI IRQ
> + * @soc: pointer to SoC-dependent operations
>    */
>   struct mtk_gen3_pcie {
>   	struct device *dev;
> @@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
>   	struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
>   	struct mutex lock;
>   	DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
> +
> +	const struct mtk_pcie_soc *soc;
>   };
>   
>   /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
> @@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>   	usleep_range(10, 20);
>   
>   	/* Don't touch the hardware registers before power up */
> -	err = mtk_pcie_power_up(pcie);
> +	err = pcie->soc->power_up(pcie);
>   	if (err)
>   		return err;
>   
> @@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
>   	pcie = pci_host_bridge_priv(host);
>   
>   	pcie->dev = dev;
> +	pcie->soc = of_device_get_match_data(dev);

device_get_match_data() can also be used here :-)

Cheers,
Angelo

Re: [PATCH 2/4] PCI: mediatek-gen3: Add mtk_pcie_soc data structure

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 2590 bytes --]

> Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> > Introduce mtk_pcie_soc data structure in order to define multiple
> > callbacks for each supported SoC. This is a preliminary patch to
> > introduce EN7581 pcie support.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
> >   1 file changed, 21 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 975b3024fb08..4859bd875bc4 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -100,6 +100,16 @@
> >   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
> >   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
> > +struct mtk_gen3_pcie;
> > +
> > +/**
> > + * struct mtk_pcie_soc - differentiate between host generations
> 
> mtk_gen3_pcie_pdata ?

ack, I will fix it in v2.

> 
> > + * @power_up: pcie power_up callback
> > + */
> > +struct mtk_pcie_soc {
> > +	int (*power_up)(struct mtk_gen3_pcie *pcie);
> > +};
> > +
> >   /**
> >    * struct mtk_msi_set - MSI information for each set
> >    * @base: IO mapped register base
> > @@ -131,6 +141,7 @@ struct mtk_msi_set {
> >    * @msi_sets: MSI sets information
> >    * @lock: lock protecting IRQ bit map
> >    * @msi_irq_in_use: bit map for assigned MSI IRQ
> > + * @soc: pointer to SoC-dependent operations
> >    */
> >   struct mtk_gen3_pcie {
> >   	struct device *dev;
> > @@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
> >   	struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
> >   	struct mutex lock;
> >   	DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
> > +
> > +	const struct mtk_pcie_soc *soc;
> >   };
> >   /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
> > @@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> >   	usleep_range(10, 20);
> >   	/* Don't touch the hardware registers before power up */
> > -	err = mtk_pcie_power_up(pcie);
> > +	err = pcie->soc->power_up(pcie);
> >   	if (err)
> >   		return err;
> > @@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
> >   	pcie = pci_host_bridge_priv(host);
> >   	pcie->dev = dev;
> > +	pcie->soc = of_device_get_match_data(dev);
> 
> device_get_match_data() can also be used here :-)

ack, I will fix it in v2.

Regards,
Lorenzo

> 
> Cheers,
> Angelo
> 

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[PATCH 3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

[Lorenzo Bianconi]

Use reset_bulk APIs to manage phy reset lines. This is a preliminary
patch in order to add Airoha EN7581 pcie support.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
 1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 4859bd875bc4..9842617795a9 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -100,14 +100,21 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
+#define MAX_NUM_PHY_RSTS		1
+
 struct mtk_gen3_pcie;
 
 /**
  * struct mtk_pcie_soc - differentiate between host generations
  * @power_up: pcie power_up callback
+ * @phy_resets: phy reset lines SoC data.
  */
 struct mtk_pcie_soc {
 	int (*power_up)(struct mtk_gen3_pcie *pcie);
+	struct {
+		const char *id[MAX_NUM_PHY_RSTS];
+		int num_rsts;
+	} phy_resets;
 };
 
 /**
@@ -128,7 +135,7 @@ struct mtk_msi_set {
  * @base: IO mapped register base
  * @reg_base: physical register base
  * @mac_reset: MAC reset control
- * @phy_reset: PHY reset control
+ * @phy_resets: PHY reset controllers
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
@@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
 	void __iomem *base;
 	phys_addr_t reg_base;
 	struct reset_control *mac_reset;
-	struct reset_control *phy_reset;
+	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
 	struct phy *phy;
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -790,8 +797,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
+	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts;
 	struct resource *regs;
-	int ret;
 
 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
 	if (!regs)
@@ -804,12 +811,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 
 	pcie->reg_base = regs->start;
 
-	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
-	if (IS_ERR(pcie->phy_reset)) {
-		ret = PTR_ERR(pcie->phy_reset);
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to get PHY reset\n");
+	for (i = 0; i < num_rsts; i++)
+		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
 
+	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
+							  pcie->phy_resets);
+	if (ret) {
+		dev_err(dev, "failed to get PHY bulk reset\n");
 		return ret;
 	}
 
@@ -846,7 +854,12 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 	int err;
 
 	/* PHY power on and enable pipe clock */
-	reset_control_deassert(pcie->phy_reset);
+	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
+					  pcie->phy_resets);
+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		return err;
+	}
 
 	err = phy_init(pcie->phy);
 	if (err) {
@@ -882,7 +895,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 err_phy_on:
 	phy_exit(pcie->phy);
 err_phy_init:
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
 
 	return err;
 }
@@ -897,7 +911,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
 
 	phy_power_off(pcie->phy);
 	phy_exit(pcie->phy);
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
 }
 
 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
@@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	 * The controller may have been left out of reset by the bootloader
 	 * so make sure that we get a clean start by asserting resets here.
 	 */
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
+				    pcie->phy_resets);
+	usleep_range(5000, 10000);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
+	msleep(100);
+
 	reset_control_assert(pcie->mac_reset);
 	usleep_range(10, 20);
 
@@ -1090,6 +1111,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
 
 static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
 	.power_up = mtk_pcie_power_up,
+	.phy_resets = {
+		.id[0] = "phy",
+		.num_rsts = 1,
+	},
 };
 
 static const struct of_device_id mtk_pcie_of_match[] = {
-- 
2.45.2

Re: [PATCH 3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

[Bjorn Helgaas]

On Fri, Jun 21, 2024 at 04:48:49PM +0200, Lorenzo Bianconi wrote:
> Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> patch in order to add Airoha EN7581 pcie support.

If you have occasion to revise this:

  s/rely/Rely/ in subject
  s/phy/PHY/ in subject and commit log
  s/pcie/PCIe/ in commit log

> @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>  	 * The controller may have been left out of reset by the bootloader
>  	 * so make sure that we get a clean start by asserting resets here.
>  	 */
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +				    pcie->phy_resets);
> +	usleep_range(5000, 10000);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);
> +	msleep(100);

Where did these usleep and msleep numbers come from?  They should use
a #define that we can connect back to a spec.

These delays should also be mentioned in the commit log because it
appears unrelated to the conversion to the reset_bulk API.  Actually,
it would be even better if they were in a separate patch, since it
looks like a logically separate change.

>  	reset_control_assert(pcie->mac_reset);
>  	usleep_range(10, 20);

Unrelated to this patch, but it would be nice to have an explanation
of this existing delay, too.

Bjorn

Re: [PATCH 3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 2080 bytes --]

> On Fri, Jun 21, 2024 at 04:48:49PM +0200, Lorenzo Bianconi wrote:
> > Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> > patch in order to add Airoha EN7581 pcie support.
> 
> If you have occasion to revise this:
> 
>   s/rely/Rely/ in subject
>   s/phy/PHY/ in subject and commit log
>   s/pcie/PCIe/ in commit log

ack, I will fix them in v2

> 
> > @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> >  	 * The controller may have been left out of reset by the bootloader
> >  	 * so make sure that we get a clean start by asserting resets here.
> >  	 */
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +				    pcie->phy_resets);
> > +	usleep_range(5000, 10000);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> > +	msleep(100);
> 
> Where did these usleep and msleep numbers come from?  They should use
> a #define that we can connect back to a spec.

I think we can get rid of the first usleep_range() since we need to
deassert the line just to avoid unbalance in deassert_count counter since the
reset line is shared (the line is actually already de-assert). I will add a
comment to clarify it.

> 
> These delays should also be mentioned in the commit log because it
> appears unrelated to the conversion to the reset_bulk API.  Actually,
> it would be even better if they were in a separate patch, since it
> looks like a logically separate change.

Regarding the msleep(100), it is not documented in the vendor sdk, I think it
necessary to complete the reset before initialize the pcie-phy. Since it is
required just for EN7581, I guess we can move it in mtk_pcie_en7581_power_up()
(in patch 4/4) before the phy_init(). What do you think?

Regards,
Lorenzo

> 
> >  	reset_control_assert(pcie->mac_reset);
> >  	usleep_range(10, 20);
> 
> Unrelated to this patch, but it would be nice to have an explanation
> of this existing delay, too.
> 
> Bjorn

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Re: [PATCH 3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

[AngeloGioacchino Del Regno]

Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> patch in order to add Airoha EN7581 pcie support.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
>   1 file changed, 37 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 4859bd875bc4..9842617795a9 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -100,14 +100,21 @@
>   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>   
> +#define MAX_NUM_PHY_RSTS		1
> +
>   struct mtk_gen3_pcie;
>   
>   /**
>    * struct mtk_pcie_soc - differentiate between host generations
>    * @power_up: pcie power_up callback
> + * @phy_resets: phy reset lines SoC data.
>    */
>   struct mtk_pcie_soc {
>   	int (*power_up)(struct mtk_gen3_pcie *pcie);
> +	struct {
> +		const char *id[MAX_NUM_PHY_RSTS];
> +		int num_rsts;

Well, it's just two chars after all, so "num_resets" looks better imo.

> +	} phy_resets;
>   };
>   
>   /**
> @@ -128,7 +135,7 @@ struct mtk_msi_set {
>    * @base: IO mapped register base
>    * @reg_base: physical register base
>    * @mac_reset: MAC reset control
> - * @phy_reset: PHY reset control
> + * @phy_resets: PHY reset controllers
>    * @phy: PHY controller block
>    * @clks: PCIe clocks
>    * @num_clks: PCIe clocks count for this port
> @@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
>   	void __iomem *base;
>   	phys_addr_t reg_base;
>   	struct reset_control *mac_reset;
> -	struct reset_control *phy_reset;
> +	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
>   	struct phy *phy;
>   	struct clk_bulk_data *clks;
>   	int num_clks;
> @@ -790,8 +797,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
>   {
>   	struct device *dev = pcie->dev;
>   	struct platform_device *pdev = to_platform_device(dev);
> +	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts; >   	struct resource *regs;
> -	int ret;
>   
>   	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
>   	if (!regs)
> @@ -804,12 +811,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
>   
>   	pcie->reg_base = regs->start;
>   
> -	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
> -	if (IS_ERR(pcie->phy_reset)) {
> -		ret = PTR_ERR(pcie->phy_reset);
> -		if (ret != -EPROBE_DEFER)
> -			dev_err(dev, "failed to get PHY reset\n");
> +	for (i = 0; i < num_rsts; i++)
> +		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
>   
> +	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
> +							  pcie->phy_resets);

92 columns is ok, you can use one line for that.

> +	if (ret) {
> +		dev_err(dev, "failed to get PHY bulk reset\n");
>   		return ret;
>   	}
>   
> @@ -846,7 +854,12 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>   	int err;
>   
>   	/* PHY power on and enable pipe clock */
> -	reset_control_deassert(pcie->phy_reset);
> +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +					  pcie->phy_resets);
> +	if (err) {
> +		dev_err(dev, "failed to deassert PHYs\n");
> +		return err;
> +	}
>   
>   	err = phy_init(pcie->phy);
>   	if (err) {
> @@ -882,7 +895,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>   err_phy_on:
>   	phy_exit(pcie->phy);
>   err_phy_init:
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

same here

>   
>   	return err;
>   }
> @@ -897,7 +911,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
>   
>   	phy_power_off(pcie->phy);
>   	phy_exit(pcie->phy);
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

ditto

>   }
>   
>   static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>   	 * The controller may have been left out of reset by the bootloader
>   	 * so make sure that we get a clean start by asserting resets here.
>   	 */
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +				    pcie->phy_resets);

and again...

> +	usleep_range(5000, 10000);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

.... :-)

Cheers,
Angelo

> +	msleep(100);
> +
>   	reset_control_assert(pcie->mac_reset);
>   	usleep_range(10, 20);
>   
> @@ -1090,6 +1111,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
>   
>   static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
>   	.power_up = mtk_pcie_power_up,
> +	.phy_resets = {
> +		.id[0] = "phy",
> +		.num_rsts = 1,
> +	},
>   };
>   
>   static const struct of_device_id mtk_pcie_of_match[] = {

Re: [PATCH 3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 5656 bytes --]

> Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> > Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> > patch in order to add Airoha EN7581 pcie support.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
> >   1 file changed, 37 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 4859bd875bc4..9842617795a9 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -100,14 +100,21 @@
> >   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
> >   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
> > +#define MAX_NUM_PHY_RSTS		1
> > +
> >   struct mtk_gen3_pcie;
> >   /**
> >    * struct mtk_pcie_soc - differentiate between host generations
> >    * @power_up: pcie power_up callback
> > + * @phy_resets: phy reset lines SoC data.
> >    */
> >   struct mtk_pcie_soc {
> >   	int (*power_up)(struct mtk_gen3_pcie *pcie);
> > +	struct {
> > +		const char *id[MAX_NUM_PHY_RSTS];
> > +		int num_rsts;
> 
> Well, it's just two chars after all, so "num_resets" looks better imo.

ack, fine. Naming is always hard :)

> 
> > +	} phy_resets;
> >   };
> >   /**
> > @@ -128,7 +135,7 @@ struct mtk_msi_set {
> >    * @base: IO mapped register base
> >    * @reg_base: physical register base
> >    * @mac_reset: MAC reset control
> > - * @phy_reset: PHY reset control
> > + * @phy_resets: PHY reset controllers
> >    * @phy: PHY controller block
> >    * @clks: PCIe clocks
> >    * @num_clks: PCIe clocks count for this port
> > @@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
> >   	void __iomem *base;
> >   	phys_addr_t reg_base;
> >   	struct reset_control *mac_reset;
> > -	struct reset_control *phy_reset;
> > +	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
> >   	struct phy *phy;
> >   	struct clk_bulk_data *clks;
> >   	int num_clks;
> > @@ -790,8 +797,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> >   {
> >   	struct device *dev = pcie->dev;
> >   	struct platform_device *pdev = to_platform_device(dev);
> > +	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts; >   	struct resource *regs;
> > -	int ret;
> >   	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
> >   	if (!regs)
> > @@ -804,12 +811,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> >   	pcie->reg_base = regs->start;
> > -	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
> > -	if (IS_ERR(pcie->phy_reset)) {
> > -		ret = PTR_ERR(pcie->phy_reset);
> > -		if (ret != -EPROBE_DEFER)
> > -			dev_err(dev, "failed to get PHY reset\n");
> > +	for (i = 0; i < num_rsts; i++)
> > +		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
> > +	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
> > +							  pcie->phy_resets);
> 
> 92 columns is ok, you can use one line for that.

I usually prefer to stay below 79 column limit, but I do not have a strong
opinion about it. I will fix it and even all below.

Regards,
Lorenzo

> 
> > +	if (ret) {
> > +		dev_err(dev, "failed to get PHY bulk reset\n");
> >   		return ret;
> >   	}
> > @@ -846,7 +854,12 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
> >   	int err;
> >   	/* PHY power on and enable pipe clock */
> > -	reset_control_deassert(pcie->phy_reset);
> > +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +					  pcie->phy_resets);
> > +	if (err) {
> > +		dev_err(dev, "failed to deassert PHYs\n");
> > +		return err;
> > +	}
> >   	err = phy_init(pcie->phy);
> >   	if (err) {
> > @@ -882,7 +895,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
> >   err_phy_on:
> >   	phy_exit(pcie->phy);
> >   err_phy_init:
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> same here
> 
> >   	return err;
> >   }
> > @@ -897,7 +911,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
> >   	phy_power_off(pcie->phy);
> >   	phy_exit(pcie->phy);
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> ditto
> 
> >   }
> >   static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> > @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> >   	 * The controller may have been left out of reset by the bootloader
> >   	 * so make sure that we get a clean start by asserting resets here.
> >   	 */
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +				    pcie->phy_resets);
> 
> and again...
> 
> > +	usleep_range(5000, 10000);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> .... :-)
> 
> Cheers,
> Angelo
> 
> > +	msleep(100);
> > +
> >   	reset_control_assert(pcie->mac_reset);
> >   	usleep_range(10, 20);
> > @@ -1090,6 +1111,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
> >   static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
> >   	.power_up = mtk_pcie_power_up,
> > +	.phy_resets = {
> > +		.id[0] = "phy",
> > +		.num_rsts = 1,
> > +	},
> >   };
> >   static const struct of_device_id mtk_pcie_of_match[] = {
> 

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[PATCH 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Lorenzo Bianconi]

Introduce support for Airoha EN7581 pcie controller to mediatek-gen3
pcie controller driver.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/Kconfig              |  2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++-
 2 files changed, 84 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index e534c02ee34f..3bd6c9430010 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -196,7 +196,7 @@ config PCIE_MEDIATEK
 
 config PCIE_MEDIATEK_GEN3
 	tristate "MediaTek Gen3 PCIe controller"
-	depends on ARCH_MEDIATEK || COMPILE_TEST
+	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
 	depends on PCI_MSI
 	help
 	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 9842617795a9..2dacfed665c6 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/irq.h>
@@ -21,6 +22,8 @@
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
+#include <linux/of_pci.h>
+#include <linux/of_device.h>
 
 #include "../pci.h"
 
@@ -29,6 +32,7 @@
 #define PCI_CLASS(class)		(class << 8)
 #define PCIE_RC_MODE			BIT(0)
 
+#define PCIE_EQ_PRESET_01_REF		0x100
 #define PCIE_CFGNUM_REG			0x140
 #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7, 0))
 #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
@@ -68,6 +72,7 @@
 #define PCIE_MSI_SET_ENABLE_REG		0x190
 #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1, 0)
 
+#define PCIE_PIPE4_PIE8_REG		0x338
 #define PCIE_MSI_SET_BASE_REG		0xc00
 #define PCIE_MSI_SET_OFFSET		0x10
 #define PCIE_MSI_SET_STATUS_OFFSET	0x04
@@ -100,7 +105,7 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
-#define MAX_NUM_PHY_RSTS		1
+#define MAX_NUM_PHY_RSTS		3
 
 struct mtk_gen3_pcie;
 
@@ -848,6 +853,72 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 	return 0;
 }
 
+static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
+{
+	struct device *dev = pcie->dev;
+	int err;
+
+	writel_relaxed(0x23020133, pcie->base + 0x10044);
+	writel_relaxed(0x50500032, pcie->base + 0x15030);
+	writel_relaxed(0x50500032, pcie->base + 0x15130);
+
+	err = phy_init(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to initialize PHY\n");
+		return err;
+	}
+	mdelay(30);
+
+	err = phy_power_on(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to power on PHY\n");
+		goto err_phy_on;
+	}
+
+	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
+					  pcie->phy_resets);
+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		goto err_phy_deassert;
+	}
+	usleep_range(5000, 10000);
+
+	pm_runtime_enable(dev);
+	pm_runtime_get_sync(dev);
+
+	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_prepare;
+	}
+
+	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
+	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
+	mdelay(10);
+
+	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_enable;
+	}
+
+	return 0;
+
+err_clk_enable:
+	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
+err_clk_prepare:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
+err_phy_deassert:
+	phy_power_off(pcie->phy);
+err_phy_on:
+	phy_exit(pcie->phy);
+
+	return err;
+}
+
 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
@@ -1117,8 +1188,19 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
 	},
 };
 
+static const struct mtk_pcie_soc mtk_pcie_soc_en7581 = {
+	.power_up = mtk_pcie_en7581_power_up,
+	.phy_resets = {
+		.id[0] = "phy-lane0",
+		.id[1] = "phy-lane1",
+		.id[2] = "phy-lane2",
+		.num_rsts = 3,
+	},
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
 	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
+	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
-- 
2.45.2

Re: [PATCH 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Bjorn Helgaas]

On Fri, Jun 21, 2024 at 04:48:50PM +0200, Lorenzo Bianconi wrote:
> Introduce support for Airoha EN7581 pcie controller to mediatek-gen3
> pcie controller driver.

s/pcie/PCIe/ (twice)

> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  drivers/pci/controller/Kconfig              |  2 +-
>  drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++-
>  2 files changed, 84 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index e534c02ee34f..3bd6c9430010 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
>  
>  config PCIE_MEDIATEK_GEN3
>  	tristate "MediaTek Gen3 PCIe controller"
> -	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
>  	depends on PCI_MSI
>  	help
>  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 9842617795a9..2dacfed665c6 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -7,6 +7,7 @@
>   */
>  
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/delay.h>
>  #include <linux/iopoll.h>
>  #include <linux/irq.h>
> @@ -21,6 +22,8 @@
>  #include <linux/pm_domain.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/reset.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_device.h>

Existing list of includes is sorted.  Preserve that sorted order.

> +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> +{
> +	struct device *dev = pcie->dev;
> +	int err;
> +
> +	writel_relaxed(0x23020133, pcie->base + 0x10044);
> +	writel_relaxed(0x50500032, pcie->base + 0x15030);
> +	writel_relaxed(0x50500032, pcie->base + 0x15130);

Magic.  Needs #defines at least for the registers.  These offsets are
HUGE, far bigger than the existing offsets:

  #define PCIE_CFGNUM_REG                 0x140
  #define PCIE_CFG_OFFSET_ADDR            0x1000
  #define PCIE_TRANS_TABLE_BASE_REG       0x800
  #define PCIE_MSI_SET_BASE_REG           0xc00
  #define PCIE_MSI_SET_ADDR_HI_BASE       0xc80
  #define PCIE_MSI_SET_ENABLE_REG         0x190
  #define PCIE_INT_ENABLE_REG             0x180
  #define PCIE_SETTING_REG                0x80
  #define PCIE_PCI_IDS_1                  0x9c
  #define PCIE_MISC_CTRL_REG              0x348
  #define PCIE_RST_CTRL_REG               0x148
  #define PCIE_LINK_STATUS_REG            0x154
  #define PCIE_LTSSM_STATUS_REG           0x150
  #define PCIE_INT_STATUS_REG             0x184

> +	err = phy_init(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to initialize PHY\n");
> +		return err;
> +	}
> +	mdelay(30);

Source?  Cite the spec that requires this delay and add a #define if
possible.

> +	err = phy_power_on(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to power on PHY\n");
> +		goto err_phy_on;
> +	}
> +
> +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +					  pcie->phy_resets);
> +	if (err) {
> +		dev_err(dev, "failed to deassert PHYs\n");
> +		goto err_phy_deassert;
> +	}
> +	usleep_range(5000, 10000);

Source?

> +	pm_runtime_enable(dev);
> +	pm_runtime_get_sync(dev);
> +
> +	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> +	if (err) {
> +		dev_err(dev, "failed to prepare clock\n");
> +		goto err_clk_prepare;
> +	}
> +
> +	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
> +	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
> +	mdelay(10);

Source?

Re: [PATCH 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 4497 bytes --]

> On Fri, Jun 21, 2024 at 04:48:50PM +0200, Lorenzo Bianconi wrote:
> > Introduce support for Airoha EN7581 pcie controller to mediatek-gen3
> > pcie controller driver.
> 
> s/pcie/PCIe/ (twice)
> 

ack, I will fix them in v2

> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  drivers/pci/controller/Kconfig              |  2 +-
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++-
> >  2 files changed, 84 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index e534c02ee34f..3bd6c9430010 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
> >  
> >  config PCIE_MEDIATEK_GEN3
> >  	tristate "MediaTek Gen3 PCIe controller"
> > -	depends on ARCH_MEDIATEK || COMPILE_TEST
> > +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
> >  	depends on PCI_MSI
> >  	help
> >  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 9842617795a9..2dacfed665c6 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -7,6 +7,7 @@
> >   */
> >  
> >  #include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> >  #include <linux/delay.h>
> >  #include <linux/iopoll.h>
> >  #include <linux/irq.h>
> > @@ -21,6 +22,8 @@
> >  #include <linux/pm_domain.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/reset.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_device.h>
> 
> Existing list of includes is sorted.  Preserve that sorted order.

ack, I will fix them in v2

> 
> > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> > +{
> > +	struct device *dev = pcie->dev;
> > +	int err;
> > +
> > +	writel_relaxed(0x23020133, pcie->base + 0x10044);
> > +	writel_relaxed(0x50500032, pcie->base + 0x15030);
> > +	writel_relaxed(0x50500032, pcie->base + 0x15130);
> 
> Magic.  Needs #defines at least for the registers.  These offsets are
> HUGE, far bigger than the existing offsets:

ack. Anyway they are in pcie mapped regions (I have not posted the dts changes
yet):

pcie0: reg = <0x0 0x1fc00000 0x0 0x20000>;
pcie1: reg = <0x0 0x1fc20000 0x0 0x20000>;

But they are undocumented. I will try to get some info for them.

> 
>   #define PCIE_CFGNUM_REG                 0x140
>   #define PCIE_CFG_OFFSET_ADDR            0x1000
>   #define PCIE_TRANS_TABLE_BASE_REG       0x800
>   #define PCIE_MSI_SET_BASE_REG           0xc00
>   #define PCIE_MSI_SET_ADDR_HI_BASE       0xc80
>   #define PCIE_MSI_SET_ENABLE_REG         0x190
>   #define PCIE_INT_ENABLE_REG             0x180
>   #define PCIE_SETTING_REG                0x80
>   #define PCIE_PCI_IDS_1                  0x9c
>   #define PCIE_MISC_CTRL_REG              0x348
>   #define PCIE_RST_CTRL_REG               0x148
>   #define PCIE_LINK_STATUS_REG            0x154
>   #define PCIE_LTSSM_STATUS_REG           0x150
>   #define PCIE_INT_STATUS_REG             0x184
> 
> > +	err = phy_init(pcie->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to initialize PHY\n");
> > +		return err;
> > +	}
> > +	mdelay(30);
> 
> Source?  Cite the spec that requires this delay and add a #define if
> possible.

They are undocumented in the vendor sdk, I will try some info for them (and
even for the ones below).

Regards,
Lorenzo

> 
> > +	err = phy_power_on(pcie->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to power on PHY\n");
> > +		goto err_phy_on;
> > +	}
> > +
> > +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +					  pcie->phy_resets);
> > +	if (err) {
> > +		dev_err(dev, "failed to deassert PHYs\n");
> > +		goto err_phy_deassert;
> > +	}
> > +	usleep_range(5000, 10000);
> 
> Source?
> 
> > +	pm_runtime_enable(dev);
> > +	pm_runtime_get_sync(dev);
> > +
> > +	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> > +	if (err) {
> > +		dev_err(dev, "failed to prepare clock\n");
> > +		goto err_clk_prepare;
> > +	}
> > +
> > +	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
> > +	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
> > +	mdelay(10);
> 
> Source?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[AngeloGioacchino Del Regno]

Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> Introduce support for Airoha EN7581 pcie controller to mediatek-gen3
> pcie controller driver.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   drivers/pci/controller/Kconfig              |  2 +-
>   drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++-
>   2 files changed, 84 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index e534c02ee34f..3bd6c9430010 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
>   
>   config PCIE_MEDIATEK_GEN3
>   	tristate "MediaTek Gen3 PCIe controller"
> -	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
>   	depends on PCI_MSI
>   	help
>   	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 9842617795a9..2dacfed665c6 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -7,6 +7,7 @@
>    */
>   
>   #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>   #include <linux/delay.h>
>   #include <linux/iopoll.h>
>   #include <linux/irq.h>
> @@ -21,6 +22,8 @@
>   #include <linux/pm_domain.h>
>   #include <linux/pm_runtime.h>
>   #include <linux/reset.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_device.h>
>   
>   #include "../pci.h"
>   
> @@ -29,6 +32,7 @@
>   #define PCI_CLASS(class)		(class << 8)
>   #define PCIE_RC_MODE			BIT(0)
>   
> +#define PCIE_EQ_PRESET_01_REF		0x100
>   #define PCIE_CFGNUM_REG			0x140
>   #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7, 0))
>   #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
> @@ -68,6 +72,7 @@
>   #define PCIE_MSI_SET_ENABLE_REG		0x190
>   #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1, 0)
>   
> +#define PCIE_PIPE4_PIE8_REG		0x338
>   #define PCIE_MSI_SET_BASE_REG		0xc00
>   #define PCIE_MSI_SET_OFFSET		0x10
>   #define PCIE_MSI_SET_STATUS_OFFSET	0x04
> @@ -100,7 +105,7 @@
>   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>   
> -#define MAX_NUM_PHY_RSTS		1
> +#define MAX_NUM_PHY_RSTS		3
>   
>   struct mtk_gen3_pcie;
>   
> @@ -848,6 +853,72 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
>   	return 0;
>   }
>   
> +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> +{
> +	struct device *dev = pcie->dev;
> +	int err;
> +
> +	writel_relaxed(0x23020133, pcie->base + 0x10044);
> +	writel_relaxed(0x50500032, pcie->base + 0x15030);
> +	writel_relaxed(0x50500032, pcie->base + 0x15130);

Can anyone from MediaTek/Airoha help to identify those registers and the layout so
that we can avoid using magic numbers around?

Please.

Regards,
Angelo

> +
> +	err = phy_init(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to initialize PHY\n");
> +		return err;
> +	}
> +	mdelay(30);
> +
> +	err = phy_power_on(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to power on PHY\n");
> +		goto err_phy_on;
> +	}
> +
> +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +					  pcie->phy_resets);
> +	if (err) {
> +		dev_err(dev, "failed to deassert PHYs\n");
> +		goto err_phy_deassert;
> +	}
> +	usleep_range(5000, 10000);
> +
> +	pm_runtime_enable(dev);
> +	pm_runtime_get_sync(dev);
> +
> +	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> +	if (err) {
> +		dev_err(dev, "failed to prepare clock\n");
> +		goto err_clk_prepare;
> +	}
> +
> +	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
> +	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
> +	mdelay(10);
> +
> +	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
> +	if (err) {
> +		dev_err(dev, "failed to prepare clock\n");
> +		goto err_clk_enable;
> +	}
> +
> +	return 0;
> +
> +err_clk_enable:
> +	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
> +err_clk_prepare:
> +	pm_runtime_put_sync(dev);
> +	pm_runtime_disable(dev);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);
> +err_phy_deassert:
> +	phy_power_off(pcie->phy);
> +err_phy_on:
> +	phy_exit(pcie->phy);
> +
> +	return err;
> +}
> +
>   static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>   {
>   	struct device *dev = pcie->dev;
> @@ -1117,8 +1188,19 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
>   	},
>   };
>   
> +static const struct mtk_pcie_soc mtk_pcie_soc_en7581 = {
> +	.power_up = mtk_pcie_en7581_power_up,
> +	.phy_resets = {
> +		.id[0] = "phy-lane0",
> +		.id[1] = "phy-lane1",
> +		.id[2] = "phy-lane2",
> +		.num_rsts = 3,
> +	},
> +};
> +
>   static const struct of_device_id mtk_pcie_of_match[] = {
>   	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
> +	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);