From: Krzysztof Kozlowski <krzk@kernel.org>
To: weishangjuan@eswincomputing.com, devicetree@vger.kernel.org,
andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com,
alexandre.torgue@foss.st.com, yong.liang.choong@linux.intel.com,
vladimir.oltean@nxp.com, rmk+kernel@armlinux.org.uk,
faizal.abdul.rahim@linux.intel.com,
prabhakar.mahadev-lad.rj@bp.renesas.com, inochiama@gmail.com,
jan.petrous@oss.nxp.com, jszhang@kernel.org,
p.zabel@pengutronix.de, boon.khai.ng@altera.com,
0x1207@gmail.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com,
lizhi2@eswincomputing.com
Subject: Re: [PATCH v4 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC
Date: Wed, 27 Aug 2025 14:48:58 +0200 [thread overview]
Message-ID: <f093fc68-c783-41eb-b51e-e48a18e6d2cf@kernel.org> (raw)
In-Reply-To: <20250827081314.2295-1-weishangjuan@eswincomputing.com>
On 27/08/2025 10:13, weishangjuan@eswincomputing.com wrote:
> + clocks:
> + items:
> + - description: GMAC main clock
> + - description: Tx clock
> + - description: AXI clock
> + - description: Configuration clock
> +
> + clock-names:
> + contains:
This part did not improve:
items: instead
> + enum:
> + - axi
> + - cfg
> + - stmmaceth
> + - tx
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: stmmaceth
> +
> + rx-internal-delay-ps:
> + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +
> + tx-internal-delay-ps:
> + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +
> + eswin,hsp-sp-csr:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - description: Phandle to HSP(High-Speed Peripheral) device
> + - description: Offset of phy control register for internal
> + or external clock selection
> + - description: Offset of AXI clock controller Low-Power request
> + register
> + - description: Offset of register controlling TX/RX clock delay
> + description: |
> + A phandle to hsp-sp-csr with three arguments that configure
> + HSP(High-Speed Peripheral) device. The argument one is the
> + offset of phy control register for internal or external clock
> + selection, the argument two is Offset of AXI clock controller
> + Low-Power request register, the argument three is Offset of
> + register controlling TX/RX clock delay.
Description is mostly redundant - it is already part of items:. Just say
here "HSP (High Spee....) device needed to configure clock selection,
clock low-power mode and clock delay." or something similar.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-27 12:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 8:11 [PATCH v4 0/2] Add driver support for Eswin eic7700 SoC ethernet controller weishangjuan
2025-08-27 8:13 ` [PATCH v4 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC weishangjuan
2025-08-27 12:48 ` Krzysztof Kozlowski [this message]
2025-08-27 8:14 ` [PATCH v4 2/2] ethernet: eswin: Add eic7700 ethernet driver weishangjuan
2025-08-27 8:24 ` Russell King (Oracle)
2025-08-28 10:05 ` 李志
2025-09-02 2:20 ` 李志
2025-08-27 12:37 ` Andrew Lunn
2025-08-27 12:43 ` Vadim Fedorenko
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