[PATCH 0/4] Add Global Clock Controller for MSM8940 and SDM439

[PATCH 0/4] Add Global Clock Controller for MSM8940 and SDM439

[Barnabás Czémán]

Add GCC support for MSM8940 and SDM439.

Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
Barnabás Czémán (2):
      dt-bindings: clock: qcom: Add MSM8940 Global Clock Controller
      dt-bindings: clock: qcom: Add SDM439 Global Clock Controller

Lanik (2):
      clk: qcom: gcc: Add support for Global Clock controller found on MSM8940
      clk: qcom: gcc: Add support for Global Clock controller found on SDM439

 .../bindings/clock/qcom,gcc-msm8953.yaml           |   6 +-
 drivers/clk/qcom/Kconfig                           |   6 +-
 drivers/clk/qcom/gcc-msm8917.c                     | 286 +++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8917.h       |   1 +
 4 files changed, 294 insertions(+), 5 deletions(-)
---
base-commit: cad72a2aa582a0ca182ef1977dc45ff2a0bfb71e
change-id: 20251116-gcc-msm8940-sdm439-4369dd6cbc16

Best regards,
-- 
Barnabás Czémán <barnabas.czeman@mainlining.org>

[PATCH 1/4] dt-bindings: clock: qcom: Add MSM8940 Global Clock Controller

[Barnabás Czémán]

Add devicetree bindings for the global clock controller on Qualcomm
MSM8940 platform.

Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 5 +++--
 include/dt-bindings/clock/qcom,gcc-msm8917.h                  | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
index f2e37f439d28..68fcd0d6492f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Global Clock & Reset Controller on MSM8953
+title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940 and MSM8953
 
 maintainers:
   - Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
 
 description: |
   Qualcomm global clock control module provides the clocks, resets and power
-  domains on MSM8937 or MSM8953.
+  domains on MSM8937, MSM8940 or MSM8953.
 
   See also::
     include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -23,6 +23,7 @@ properties:
   compatible:
     enum:
       - qcom,gcc-msm8937
+      - qcom,gcc-msm8940
       - qcom,gcc-msm8953
 
   clocks:
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h
index 4e3897b3669d..066acb447f4f 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8917.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -187,6 +187,7 @@
 #define MSM8937_GCC_MDSS_PCLK1_CLK			179
 #define MSM8937_GCC_OXILI_AON_CLK			180
 #define MSM8937_GCC_OXILI_TIMER_CLK			181
+#define MSM8940_GCC_IPA_TBU_CLK				182
 
 /* GCC block resets */
 #define GCC_CAMSS_MICRO_BCR			0

-- 
2.51.2

[PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Barnabás Czémán]

From: Lanik <daniilt971@gmail.com>

Modify existing MSM8917 driver to support MSM8940 SoC. MSM8940 SoC has the
same changes as MSM8937 SoC, but with additional IPA clk and different
GFX3D clock frequency table.

Signed-off-by: Lanik <daniilt971@gmail.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
 drivers/clk/qcom/Kconfig       |   6 +-
 drivers/clk/qcom/gcc-msm8917.c | 231 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 234 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 4a78099e706c..c2c62b3a5bdc 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -370,12 +370,12 @@ config MSM_GCC_8916
 	  SD/eMMC, display, graphics, camera etc.
 
 config MSM_GCC_8917
-	tristate "MSM89(17/37)/QM215 Global Clock Controller"
+	tristate "MSM89(17/37/40)/QM215 Global Clock Controller"
 	depends on ARM64 || COMPILE_TEST
 	select QCOM_GDSC
 	help
-	  Support for the global clock controller on msm8917, msm8937
-	  and qm215 devices.
+	  Support for the global clock controller on msm8917, msm8937,
+	  msm8940 and qm215 devices.
 	  Say Y if you want to use devices such as UART, SPI i2c, USB,
 	  SD/eMMC, display, graphics, camera etc.
 
diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c
index 0a1aa623cd49..6985888def5e 100644
--- a/drivers/clk/qcom/gcc-msm8917.c
+++ b/drivers/clk/qcom/gcc-msm8917.c
@@ -957,6 +957,27 @@ static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gfx3d_clk_src_msm8940[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	F(80000000, P_GPLL0, 10, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(160000000, P_GPLL0, 5, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(216000000, P_GPLL6, 5, 0, 0),
+	F(228570000, P_GPLL0, 3.5, 0, 0),
+	F(240000000, P_GPLL6, 4.5, 0, 0),
+	F(266670000, P_GPLL0, 3, 0, 0),
+	F(300000000, P_GPLL3, 1, 0, 0),
+	F(320000000, P_GPLL0, 2.5, 0, 0),
+	F(375000000, P_GPLL3, 1, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	F(450000000, P_GPLL3, 1, 0, 0),
+	F(475000000, P_GPLL3, 1, 0, 0),
+	F(500000000, P_GPLL3, 1, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 gfx3d_clk_src = {
 	.cmd_rcgr = 0x59000,
 	.hid_width = 5,
@@ -3307,6 +3328,19 @@ static struct clk_branch gcc_vfe_tbu_clk = {
 	}
 };
 
+static struct clk_branch gcc_ipa_tbu_clk = {
+	.halt_reg = 0x120a0,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x4500c,
+		.enable_mask = BIT(16),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_ipa_tbu_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct gdsc venus_gdsc = {
 	.gdscr = 0x4c018,
 	.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
@@ -3764,6 +3798,189 @@ static struct clk_regmap *gcc_msm8937_clocks[] = {
 	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
 };
 
+static struct clk_regmap *gcc_msm8940_clocks[] = {
+	[GPLL0] = &gpll0.clkr,
+	[GPLL0_EARLY] = &gpll0_early.clkr,
+	[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
+	[GPLL3] = &gpll3.clkr,
+	[GPLL3_EARLY] = &gpll3_early.clkr,
+	[GPLL4] = &gpll4.clkr,
+	[GPLL4_EARLY] = &gpll4_early.clkr,
+	[GPLL6] = &gpll6,
+	[GPLL6_EARLY] = &gpll6_early.clkr,
+	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
+	[MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+	[MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+	[MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+	[MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
+	[MSM8937_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
+	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
+	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
+	[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
+	[CCI_CLK_SRC] = &cci_clk_src.clkr,
+	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
+	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
+	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
+	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
+	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
+	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
+	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
+	[MSM8937_ESC1_CLK_SRC] = &esc1_clk_src.clkr,
+	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
+	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
+	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
+	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
+	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
+	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
+	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
+	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
+	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
+	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
+	[MSM8937_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
+	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
+	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
+	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
+	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
+	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
+	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
+	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
+	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+	[MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+	[MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+	[MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+	[MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
+	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
+	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
+	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
+	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
+	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
+	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
+	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
+	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
+	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
+	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
+	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
+	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
+	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
+	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
+	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
+	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
+	[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
+	[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
+	[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
+	[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
+	[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
+	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
+	[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
+	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
+	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
+	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
+	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
+	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
+	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
+	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
+	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
+	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
+	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
+	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
+	[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
+	[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
+	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
+	[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
+	[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
+	[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
+	[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
+	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
+	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
+	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
+	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
+	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
+	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
+	[MSM8937_GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
+	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
+	[MSM8937_GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
+	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
+	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
+	[MSM8937_GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
+	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
+	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
+	[MSM8937_GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
+	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
+	[MSM8937_GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
+	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
+	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
+	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
+	[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
+	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
+	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
+	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
+	[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
+	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
+	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
+	[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
+	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
+	[MSM8940_GCC_IPA_TBU_CLK] = &gcc_ipa_tbu_clk.clkr,
+};
+
 static const struct qcom_reset_map gcc_msm8917_resets[] = {
 	[GCC_CAMSS_MICRO_BCR]		= { 0x56008 },
 	[GCC_MSS_BCR]			= { 0x71000 },
@@ -3833,6 +4050,16 @@ static const struct qcom_cc_desc gcc_msm8937_desc = {
 	.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
 };
 
+static const struct qcom_cc_desc gcc_msm8940_desc = {
+	.config = &gcc_msm8917_regmap_config,
+	.clks = gcc_msm8940_clocks,
+	.num_clks = ARRAY_SIZE(gcc_msm8940_clocks),
+	.resets = gcc_msm8917_resets,
+	.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
+	.gdscs = gcc_msm8937_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
+};
+
 static void msm8937_clock_override(void)
 {
 	/* GPLL3 750MHz configuration */
@@ -3870,6 +4097,9 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
 	} else if (gcc_desc == &gcc_msm8937_desc) {
 		msm8937_clock_override();
 		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937;
+	} else if (gcc_desc == &gcc_msm8940_desc) {
+		msm8937_clock_override();
+		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8940;
 	}
 
 	regmap = qcom_cc_map(pdev, gcc_desc);
@@ -3885,6 +4115,7 @@ static const struct of_device_id gcc_msm8917_match_table[] = {
 	{ .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
 	{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
 	{ .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
+	{ .compatible = "qcom,gcc-msm8940", .data = &gcc_msm8940_desc },
 	{},
 };
 MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);

-- 
2.51.2

[PATCH 3/4] dt-bindings: clock: qcom: Add SDM439 Global Clock Controller

[Barnabás Czémán]

Add devicetree bindings for the global clock controller on Qualcomm
SDM439 platform.

Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
index 68fcd0d6492f..ced3118c8580 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940 and MSM8953
+title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
 
 maintainers:
   - Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
 
 description: |
   Qualcomm global clock control module provides the clocks, resets and power
-  domains on MSM8937, MSM8940 or MSM8953.
+  domains on MSM8937, MSM8940, MSM8953 or SDM439.
 
   See also::
     include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -25,6 +25,7 @@ properties:
       - qcom,gcc-msm8937
       - qcom,gcc-msm8940
       - qcom,gcc-msm8953
+      - qcom,gcc-sdm439
 
   clocks:
     items:

-- 
2.51.2

[PATCH 4/4] clk: qcom: gcc: Add support for Global Clock controller found on SDM439

[Barnabás Czémán]

From: Lanik <daniilt971@gmail.com>

Modify existing MSM8917 driver to support SDM439 SoC. SDM439 SoC has the
same changes as MSM8937 SoC, but with different gpll3 vco rate and
different GFX3D clock frequency table.

Signed-off-by: Lanik <daniilt971@gmail.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
 drivers/clk/qcom/Kconfig       |  4 +--
 drivers/clk/qcom/gcc-msm8917.c | 55 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c2c62b3a5bdc..b74f4bfcbe5e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -370,12 +370,12 @@ config MSM_GCC_8916
 	  SD/eMMC, display, graphics, camera etc.
 
 config MSM_GCC_8917
-	tristate "MSM89(17/37/40)/QM215 Global Clock Controller"
+	tristate "MSM89(17/37/40)/QM215/SDM439 Global Clock Controller"
 	depends on ARM64 || COMPILE_TEST
 	select QCOM_GDSC
 	help
 	  Support for the global clock controller on msm8917, msm8937,
-	  msm8940 and qm215 devices.
+	  msm8940, qm215 and sdm439 devices.
 	  Say Y if you want to use devices such as UART, SPI i2c, USB,
 	  SD/eMMC, display, graphics, camera etc.
 
diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c
index 6985888def5e..b6df627b0e05 100644
--- a/drivers/clk/qcom/gcc-msm8917.c
+++ b/drivers/clk/qcom/gcc-msm8917.c
@@ -978,6 +978,27 @@ static const struct freq_tbl ftbl_gfx3d_clk_src_msm8940[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gfx3d_clk_src_sdm439[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	F(80000000, P_GPLL0, 10, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(160000000, P_GPLL0, 5, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(216000000, P_GPLL6, 5, 0, 0),
+	F(228570000, P_GPLL0, 3.5, 0, 0),
+	F(240000000, P_GPLL6, 4.5, 0, 0),
+	F(266670000, P_GPLL0, 3, 0, 0),
+	F(320000000, P_GPLL0, 2.5, 0, 0),
+	F(355200000, P_GPLL3, 1, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	F(450000000, P_GPLL3, 1, 0, 0),
+	F(510000000, P_GPLL3, 1, 0, 0),
+	F(560000000, P_GPLL3, 1, 0, 0),
+	F(650000000, P_GPLL3, 1, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 gfx3d_clk_src = {
 	.cmd_rcgr = 0x59000,
 	.hid_width = 5,
@@ -4060,6 +4081,16 @@ static const struct qcom_cc_desc gcc_msm8940_desc = {
 	.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
 };
 
+static const struct qcom_cc_desc gcc_sdm439_desc = {
+	.config = &gcc_msm8917_regmap_config,
+	.clks = gcc_msm8937_clocks,
+	.num_clks = ARRAY_SIZE(gcc_msm8937_clocks),
+	.resets = gcc_msm8917_resets,
+	.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
+	.gdscs = gcc_msm8937_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
+};
+
 static void msm8937_clock_override(void)
 {
 	/* GPLL3 750MHz configuration */
@@ -4085,6 +4116,27 @@ static void msm8937_clock_override(void)
 	usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_msm8937;
 }
 
+static void sdm439_clock_override(void)
+{
+	/*
+	 * Set below clocks for use specific sdm439 parent map.
+	 */
+	vcodec0_clk_src.parent_map = gcc_cpp_map;
+	vcodec0_clk_src.clkr.hw.init = &vcodec0_clk_src_init_msm8937;
+
+	/*
+	 * Set below clocks for use specific sdm439 freq table.
+	 */
+	vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
+	vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
+	cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_msm8937;
+	vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_msm8937;
+	gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_sdm439;
+	csi0phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
+	csi1phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
+	usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_msm8937;
+}
+
 static int gcc_msm8917_probe(struct platform_device *pdev)
 {
 	struct regmap *regmap;
@@ -4100,6 +4152,8 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
 	} else if (gcc_desc == &gcc_msm8940_desc) {
 		msm8937_clock_override();
 		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8940;
+	} else if (gcc_desc == &gcc_sdm439_desc) {
+		sdm439_clock_override();
 	}
 
 	regmap = qcom_cc_map(pdev, gcc_desc);
@@ -4116,6 +4170,7 @@ static const struct of_device_id gcc_msm8917_match_table[] = {
 	{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
 	{ .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
 	{ .compatible = "qcom,gcc-msm8940", .data = &gcc_msm8940_desc },
+	{ .compatible = "qcom,gcc-sdm439", .data = &gcc_sdm439_desc },
 	{},
 };
 MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);

-- 
2.51.2

Re: [PATCH 1/4] dt-bindings: clock: qcom: Add MSM8940 Global Clock Controller

[Krzysztof Kozlowski]

On Sun, Nov 16, 2025 at 10:35:56PM +0100, Barnabás Czémán wrote:
> Add devicetree bindings for the global clock controller on Qualcomm
> MSM8940 platform.
> 
> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
> ---
>  Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 5 +++--
>  include/dt-bindings/clock/qcom,gcc-msm8917.h                  | 1 +
>  2 files changed, 4 insertions(+), 2 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: clock: qcom: Add SDM439 Global Clock Controller

[Krzysztof Kozlowski]

On Sun, Nov 16, 2025 at 10:35:58PM +0100, Barnabás Czémán wrote:
> Add devicetree bindings for the global clock controller on Qualcomm
> SDM439 platform.
> 
> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
> ---
>  Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Taniya Das]

On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>  
> +static struct clk_branch gcc_ipa_tbu_clk = {
> +	.halt_reg = 0x120a0,
> +	.halt_check = BRANCH_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x4500c,
> +		.enable_mask = BIT(16),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_ipa_tbu_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +

Is the TBU clock used on 8940 by a SMMU driver?

>  static struct gdsc venus_gdsc = {
>  	.gdscr = 0x4c018,
>  	.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
> @@ -3764,6 +3798,189 @@ static struct clk_regmap *gcc_msm8937_clocks[] = {
>  	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
>  };

-- 
Thanks,
Taniya Das

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Barnabás Czémán]

On 17 November 2025 09:03:53 CET, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>
>
>On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>  
>> +static struct clk_branch gcc_ipa_tbu_clk = {
>> +	.halt_reg = 0x120a0,
>> +	.halt_check = BRANCH_VOTED,
>> +	.clkr = {
>> +		.enable_reg = 0x4500c,
>> +		.enable_mask = BIT(16),
>> +		.hw.init = &(struct clk_init_data){
>> +			.name = "gcc_ipa_tbu_clk",
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>
>Is the TBU clock used on 8940 by a SMMU driver?
As far as I know no MSM8940 is using same smmu driver and bindings like MSM8937.
>
>>  static struct gdsc venus_gdsc = {
>>  	.gdscr = 0x4c018,
>>  	.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
>> @@ -3764,6 +3798,189 @@ static struct clk_regmap *gcc_msm8937_clocks[] = {
>>  	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
>>  };
>

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Konrad Dybcio]

On 11/17/25 9:51 AM, Barnabás Czémán wrote:
> 
> 
> On 17 November 2025 09:03:53 CET, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>
>>
>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>  
>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>> +	.halt_reg = 0x120a0,
>>> +	.halt_check = BRANCH_VOTED,
>>> +	.clkr = {
>>> +		.enable_reg = 0x4500c,
>>> +		.enable_mask = BIT(16),
>>> +		.hw.init = &(struct clk_init_data){
>>> +			.name = "gcc_ipa_tbu_clk",
>>> +			.ops = &clk_branch2_ops,
>>> +		},
>>> +	},
>>> +};
>>> +
>>
>> Is the TBU clock used on 8940 by a SMMU driver?
> As far as I know no MSM8940 is using same smmu driver and bindings like MSM8937.

On msm8939, the clock needed to be turned on for the GPU SMMU

See 5bc1cf1466f6 ("iommu/qcom: add optional 'tbu' clock for TLB invalidate")

Konrad

Re: [PATCH 4/4] clk: qcom: gcc: Add support for Global Clock controller found on SDM439

[Konrad Dybcio]

On 11/16/25 10:35 PM, Barnabás Czémán wrote:
> From: Lanik <daniilt971@gmail.com>
> 
> Modify existing MSM8917 driver to support SDM439 SoC. SDM439 SoC has the
> same changes as MSM8937 SoC, but with different gpll3 vco rate and
> different GFX3D clock frequency table.
> 
> Signed-off-by: Lanik <daniilt971@gmail.com>

This doesn't seem like a proper full name, please fix up your git
config

[...]

> +static void sdm439_clock_override(void)
> +{
> +	/*
> +	 * Set below clocks for use specific sdm439 parent map.
> +	 */
> +	vcodec0_clk_src.parent_map = gcc_cpp_map;
> +	vcodec0_clk_src.clkr.hw.init = &vcodec0_clk_src_init_msm8937;
> +
> +	/*
> +	 * Set below clocks for use specific sdm439 freq table.
> +	 */

These comments are rather self-explanatory, you can drop them

Konrad

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[barnabas.czeman]

On 2025-11-17 13:17, Konrad Dybcio wrote:
> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>> 
>> 
>> On 17 November 2025 09:03:53 CET, Taniya Das 
>> <taniya.das@oss.qualcomm.com> wrote:
>>> 
>>> 
>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>> 
>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>> +	.halt_reg = 0x120a0,
>>>> +	.halt_check = BRANCH_VOTED,
>>>> +	.clkr = {
>>>> +		.enable_reg = 0x4500c,
>>>> +		.enable_mask = BIT(16),
>>>> +		.hw.init = &(struct clk_init_data){
>>>> +			.name = "gcc_ipa_tbu_clk",
>>>> +			.ops = &clk_branch2_ops,
>>>> +		},
>>>> +	},
>>>> +};
>>>> +
>>> 
>>> Is the TBU clock used on 8940 by a SMMU driver?
>> As far as I know no MSM8940 is using same smmu driver and bindings 
>> like MSM8937.
> 
> On msm8939, the clock needed to be turned on for the GPU SMMU
I have not got any qcom-iommu issues on 8940 but i think it could come 
when i try to add ipa2 driver
for the SoC until i do not know where to check it.
> 
> See 5bc1cf1466f6 ("iommu/qcom: add optional 'tbu' clock for TLB 
> invalidate")
> 
> Konrad

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Konrad Dybcio]

On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
> On 2025-11-17 13:17, Konrad Dybcio wrote:
>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>
>>>
>>> On 17 November 2025 09:03:53 CET, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>>>
>>>>
>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>
>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>> +    .halt_reg = 0x120a0,
>>>>> +    .halt_check = BRANCH_VOTED,
>>>>> +    .clkr = {
>>>>> +        .enable_reg = 0x4500c,
>>>>> +        .enable_mask = BIT(16),
>>>>> +        .hw.init = &(struct clk_init_data){
>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>> +            .ops = &clk_branch2_ops,
>>>>> +        },
>>>>> +    },
>>>>> +};
>>>>> +
>>>>
>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>> As far as I know no MSM8940 is using same smmu driver and bindings like MSM8937.
>>
>> On msm8939, the clock needed to be turned on for the GPU SMMU
> I have not got any qcom-iommu issues on 8940 but i think it could come when i try to add ipa2 driver
> for the SoC until i do not know where to check it.

I can't find a definitive answer, but it's most certainly going to be
necessary to turn it on

Konrad

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[barnabas.czeman]

On 2025-11-17 15:17, Konrad Dybcio wrote:
> On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
>> On 2025-11-17 13:17, Konrad Dybcio wrote:
>>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>> 
>>>> 
>>>> On 17 November 2025 09:03:53 CET, Taniya Das 
>>>> <taniya.das@oss.qualcomm.com> wrote:
>>>>> 
>>>>> 
>>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>> 
>>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>>> +    .halt_reg = 0x120a0,
>>>>>> +    .halt_check = BRANCH_VOTED,
>>>>>> +    .clkr = {
>>>>>> +        .enable_reg = 0x4500c,
>>>>>> +        .enable_mask = BIT(16),
>>>>>> +        .hw.init = &(struct clk_init_data){
>>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>>> +            .ops = &clk_branch2_ops,
>>>>>> +        },
>>>>>> +    },
>>>>>> +};
>>>>>> +
>>>>> 
>>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>>> As far as I know no MSM8940 is using same smmu driver and bindings 
>>>> like MSM8937.
>>> 
>>> On msm8939, the clock needed to be turned on for the GPU SMMU
>> I have not got any qcom-iommu issues on 8940 but i think it could come 
>> when i try to add ipa2 driver
>> for the SoC until i do not know where to check it.
> 
> I can't find a definitive answer, but it's most certainly going to be
> necessary to turn it on
> 
> Konrad

I have enabled ipa2-lite for 8940 at downstream and it can cause gpu to 
crash.
I have tried to add TBU clock for apps_iommu but it not fixing the 
issue.

Here are the iommu changes based on 8937 apps_iommu node:
+&apps_iommu {
+       clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                <&gcc GCC_APSS_TCU_CLK>,
+                <&gcc MSM8940_GCC_IPA_TBU_CLK>;
+       clock-names = "iface",
+                     "bus",
+                     "tbu";
+
+       /* IPA */
+       iommu-ctx@18000 {
+               compatible = "qcom,msm-iommu-v1-ns";
+               reg = <0x18000 0x1000>;
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};
+

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Konrad Dybcio]

On 11/30/25 3:50 PM, barnabas.czeman@mainlining.org wrote:
> On 2025-11-17 15:17, Konrad Dybcio wrote:
>> On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
>>> On 2025-11-17 13:17, Konrad Dybcio wrote:
>>>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>>>
>>>>>
>>>>> On 17 November 2025 09:03:53 CET, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>>>>>
>>>>>>
>>>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>>>
>>>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>>>> +    .halt_reg = 0x120a0,
>>>>>>> +    .halt_check = BRANCH_VOTED,
>>>>>>> +    .clkr = {
>>>>>>> +        .enable_reg = 0x4500c,
>>>>>>> +        .enable_mask = BIT(16),
>>>>>>> +        .hw.init = &(struct clk_init_data){
>>>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>>>> +            .ops = &clk_branch2_ops,
>>>>>>> +        },
>>>>>>> +    },
>>>>>>> +};
>>>>>>> +
>>>>>>
>>>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>>>> As far as I know no MSM8940 is using same smmu driver and bindings like MSM8937.
>>>>
>>>> On msm8939, the clock needed to be turned on for the GPU SMMU
>>> I have not got any qcom-iommu issues on 8940 but i think it could come when i try to add ipa2 driver
>>> for the SoC until i do not know where to check it.
>>
>> I can't find a definitive answer, but it's most certainly going to be
>> necessary to turn it on
>>
>> Konrad
> 
> I have enabled ipa2-lite for 8940 at downstream and it can cause gpu to crash.

Really!?

FWIW the clock on 8939 is called GCC_*GFX*_TBU_CLK so it being related
made more sense. Here, I see no connection :/

Konrad

> I have tried to add TBU clock for apps_iommu but it not fixing the issue.
> 
> Here are the iommu changes based on 8937 apps_iommu node:
> +&apps_iommu {
> +       clocks = <&gcc GCC_SMMU_CFG_CLK>,
> +                <&gcc GCC_APSS_TCU_CLK>,
> +                <&gcc MSM8940_GCC_IPA_TBU_CLK>;
> +       clock-names = "iface",
> +                     "bus",
> +                     "tbu";
> +
> +       /* IPA */
> +       iommu-ctx@18000 {
> +               compatible = "qcom,msm-iommu-v1-ns";
> +               reg = <0x18000 0x1000>;
> +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +};
> +
> 

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[barnabas.czeman]

On 2025-12-01 13:26, Konrad Dybcio wrote:
> On 11/30/25 3:50 PM, barnabas.czeman@mainlining.org wrote:
>> On 2025-11-17 15:17, Konrad Dybcio wrote:
>>> On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
>>>> On 2025-11-17 13:17, Konrad Dybcio wrote:
>>>>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>>>> 
>>>>>> 
>>>>>> On 17 November 2025 09:03:53 CET, Taniya Das 
>>>>>> <taniya.das@oss.qualcomm.com> wrote:
>>>>>>> 
>>>>>>> 
>>>>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>>>> 
>>>>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>>>>> +    .halt_reg = 0x120a0,
>>>>>>>> +    .halt_check = BRANCH_VOTED,
>>>>>>>> +    .clkr = {
>>>>>>>> +        .enable_reg = 0x4500c,
>>>>>>>> +        .enable_mask = BIT(16),
>>>>>>>> +        .hw.init = &(struct clk_init_data){
>>>>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>>>>> +            .ops = &clk_branch2_ops,
>>>>>>>> +        },
>>>>>>>> +    },
>>>>>>>> +};
>>>>>>>> +
>>>>>>> 
>>>>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>>>>> As far as I know no MSM8940 is using same smmu driver and bindings 
>>>>>> like MSM8937.
>>>>> 
>>>>> On msm8939, the clock needed to be turned on for the GPU SMMU
>>>> I have not got any qcom-iommu issues on 8940 but i think it could 
>>>> come when i try to add ipa2 driver
>>>> for the SoC until i do not know where to check it.
>>> 
>>> I can't find a definitive answer, but it's most certainly going to be
>>> necessary to turn it on
>>> 
>>> Konrad
>> 
>> I have enabled ipa2-lite for 8940 at downstream and it can cause gpu 
>> to crash.
> 
> Really!?
> 
> FWIW the clock on 8939 is called GCC_*GFX*_TBU_CLK so it being related
> made more sense. Here, I see no connection :/
> 
> Konrad

I have find out the issue was caused by the interconnect, removing 
sync_state callback
makes the ipa driver working, the ipa tbu clock do not needed to be 
enabled by smmu.
> 
>> I have tried to add TBU clock for apps_iommu but it not fixing the 
>> issue.
>> 
>> Here are the iommu changes based on 8937 apps_iommu node:
>> +&apps_iommu {
>> +       clocks = <&gcc GCC_SMMU_CFG_CLK>,
>> +                <&gcc GCC_APSS_TCU_CLK>,
>> +                <&gcc MSM8940_GCC_IPA_TBU_CLK>;
>> +       clock-names = "iface",
>> +                     "bus",
>> +                     "tbu";
>> +
>> +       /* IPA */
>> +       iommu-ctx@18000 {
>> +               compatible = "qcom,msm-iommu-v1-ns";
>> +               reg = <0x18000 0x1000>;
>> +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> +       };
>> +};
>> +
>> 

Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[Konrad Dybcio]

On 12/2/25 2:40 PM, barnabas.czeman@mainlining.org wrote:
> On 2025-12-01 13:26, Konrad Dybcio wrote:
>> On 11/30/25 3:50 PM, barnabas.czeman@mainlining.org wrote:
>>> On 2025-11-17 15:17, Konrad Dybcio wrote:
>>>> On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
>>>>> On 2025-11-17 13:17, Konrad Dybcio wrote:
>>>>>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 17 November 2025 09:03:53 CET, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>>>>>
>>>>>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>>>>>> +    .halt_reg = 0x120a0,
>>>>>>>>> +    .halt_check = BRANCH_VOTED,
>>>>>>>>> +    .clkr = {
>>>>>>>>> +        .enable_reg = 0x4500c,
>>>>>>>>> +        .enable_mask = BIT(16),
>>>>>>>>> +        .hw.init = &(struct clk_init_data){
>>>>>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>>>>>> +            .ops = &clk_branch2_ops,
>>>>>>>>> +        },
>>>>>>>>> +    },
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>
>>>>>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>>>>>> As far as I know no MSM8940 is using same smmu driver and bindings like MSM8937.
>>>>>>
>>>>>> On msm8939, the clock needed to be turned on for the GPU SMMU
>>>>> I have not got any qcom-iommu issues on 8940 but i think it could come when i try to add ipa2 driver
>>>>> for the SoC until i do not know where to check it.
>>>>
>>>> I can't find a definitive answer, but it's most certainly going to be
>>>> necessary to turn it on
>>>>
>>>> Konrad
>>>
>>> I have enabled ipa2-lite for 8940 at downstream and it can cause gpu to crash.
>>
>> Really!?
>>
>> FWIW the clock on 8939 is called GCC_*GFX*_TBU_CLK so it being related
>> made more sense. Here, I see no connection :/
>>
>> Konrad
> 
> I have find out the issue was caused by the interconnect, removing sync_state callback
> makes the ipa driver working, the ipa tbu clock do not needed to be enabled by smmu.

That's bad. Removing .sync_state keeps *all* the interconnect resources
enabled, and more specifically pinned to their maximum performance state.

If you need to remove .sync_state, it's a good indicator that you're missing
a vote one of these ICC paths. I would imagine it's precisely the IPA-MEM one.

Konrad