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From: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
To: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Michal Simek
	<michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Cc: Dhaval Shah <dhaval.shah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
	gregkh <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
	DTML <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Linux Kernel Mailing List
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Hyun Kwon <hyunk-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
	Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
Date: Tue, 19 Dec 2017 14:24:55 +0100	[thread overview]
Message-ID: <f11d2f97-3eda-d43d-2cbd-96d2c331fd47@xilinx.com> (raw)
In-Reply-To: <CAK8P3a0z6HF8Rg08HUj7_T+7ZxxnHoReiu68bNzF6CnEooQSdA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On 18.12.2017 15:05, Arnd Bergmann wrote:
> On Mon, Dec 18, 2017 at 2:13 PM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>> On 15.12.2017 14:26, Arnd Bergmann wrote:
>>> In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah <dhaval.shah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>>>> Xilinx ZYNQMP logicoreIP Init driver is based on the new
>>>> LogiCoreIP design created. This driver provides the processing system
>>>> and programmable logic isolation. Set the frequency based on the clock
>>>> information get from the logicoreIP register set.
>>>>
>>>> It is put in drivers/misc as there is no subsystem for this logicoreIP.
>>>>
>>>> Signed-off-by: Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>>>
>>> After giving this some more thought, I'd suggest you move the driver to
>>> drivers/soc/xilinx or drivers/soc/zynq instead of drivers/misc/, and have
>>> it merged by Michal Simek as a driver patch that will go through arm-soc.
>>
>> I have not a problem of creating drivers/soc/xilinx/ location for this
>> driver. It is not zynq (arm32) but zynqmp(arm64) device where this
>> driver can be used. As far as I understand it is memory mapped soft IP
>> which could be also accessed by soft core CPU.
> 
> Ok. I wouldn't be worried about having a zynq directory for stuff that
> is common between zynq and zynqmp, but the soft code CPU case
> wouldn't make that ideal.
> 
>> It means drivers/soc/xilinx could be shared by all xilinx platforms anyway.
>> We have been discussing that openrisc cases and for sure if someone
>> wants to enable this driver there using misc location would be one
>> option but I also think that using drivers/soc/xilinx location is not a
>> bad option because it is very unlikely that anybody tries it.
>>
>> Arnd: misc or drivers/soc/xilinx?
> 
> drivers/soc/xilinx please, thanks for the clarification.
> 

ok. I have sent patch which prepare structures in drivers/soc/xilinx.

Dhaval: Please rebase your patch based on this and put driver to this
location.

Thanks,
Michal

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  parent reply	other threads:[~2017-12-19 13:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <200703.nxabyfcjbswwbp4v@rob-hp-laptop>
2017-12-14  5:55 ` [PATCH v3 0/2] Documentation and driver of logicoreIP Dhaval Shah
2017-12-14  5:55   ` [PATCH v3 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu driver Dhaval Shah
     [not found]   ` <1513230920-9005-1-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-14  5:55     ` [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
     [not found]       ` <1513230920-9005-3-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-14 18:42         ` Randy Dunlap
     [not found]           ` <29198c0a-783e-8aa0-00e4-44b1fa1acef7-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2017-12-15  6:00             ` Dhaval Rajeshbhai Shah
2017-12-15  7:24             ` [PATCH v4 0/2] Documentation and driver of logicoreIP Dhaval Shah
     [not found]               ` <1513322656-4571-1-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-15  7:24                 ` [PATCH v4 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu driver Dhaval Shah
     [not found]                   ` <1513322656-4571-2-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-16 18:20                     ` Rob Herring
2017-12-15  7:24               ` [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
     [not found]                 ` <1513322656-4571-3-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-15 13:26                   ` Arnd Bergmann
     [not found]                     ` <CAK8P3a0nm_-pxGWXHx_FAXgXt1msE2bK0D4paBMWgryPyeS9xA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-18 13:13                       ` Michal Simek
     [not found]                         ` <b3b41b04-7f93-1c20-2e62-817b4c743b89-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-18 14:05                           ` Arnd Bergmann
     [not found]                             ` <CAK8P3a0z6HF8Rg08HUj7_T+7ZxxnHoReiu68bNzF6CnEooQSdA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-19 13:24                               ` Michal Simek [this message]
2017-12-21 18:33                             ` [PATCH v6 0/2] Documentation and driver of logicoreIP Dhaval Shah
2017-12-21 18:33                               ` [PATCH v6 1/2] dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver Dhaval Shah
     [not found]                               ` <1513881186-26020-1-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-21 18:33                                 ` [PATCH v6 2/2] soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah
2018-01-08 12:43                                 ` [PATCH v6 0/2] Documentation and driver of logicoreIP Michal Simek
2017-12-16 22:18                   ` [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Randy Dunlap
     [not found]                     ` <d9e263f9-827c-656d-77fd-bbbb2b172040-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2017-12-17  6:07                       ` Dhaval Rajeshbhai Shah
     [not found]                         ` <BY2PR0201MB1879AFE10931133E229C0849C1090-xQ6P1Lmehamr4PZSg9VoqRrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-12-17 17:40                           ` Randy Dunlap
     [not found]                             ` <6758f505-2940-feb9-a14a-9d5e3962f7f2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2017-12-18  5:37                               ` Dhaval Rajeshbhai Shah
2017-12-18  6:15                               ` [PATCH v5 0/2] Documentation and driver of logicoreIP Dhaval Shah
2017-12-18  6:15                                 ` [PATCH v5 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu driver Dhaval Shah
     [not found]                                   ` <1513577732-10651-2-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-12-19 23:09                                     ` Rob Herring
2017-12-20  3:00                                       ` Dhaval Rajeshbhai Shah
2017-12-18  6:15                                 ` [PATCH v5 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Dhaval Shah

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