From: Conor Dooley <conor.dooley@microchip.com>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
<linux-riscv@lists.infradead.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Fri, 31 Mar 2023 13:24:41 +0100 [thread overview]
Message-ID: <f12f9773-77b5-4ba6-9e9e-adbc67ca0110@spud> (raw)
In-Reply-To: <20230330204217.47666-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hey,
I think most of what I wanted to talk about has been raised by Arnd or
Geert, so I kinda only have a couple of small comments for you here.
On Thu, Mar 30, 2023 at 09:42:12PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently, selecting which CMOs to use on a given platform is done using
> and ALTERNATIVE_X() macro. This was manageable when there were just two
> CMO implementations, but now that there are more and more platforms coming
> needing custom CMOs, the use of the ALTERNATIVE_X() macro is unmanageable.
>
> To avoid such issues this patch switches to use of function pointers
> instead of ALTERNATIVE_X() macro for cache management (the only drawback
> being performance over the previous approach).
>
> void (*clean_range)(unsigned long addr, unsigned long size);
> void (*inv_range)(unsigned long addr, unsigned long size);
> void (*flush_range)(unsigned long addr, unsigned long size);
So, given Arnd has renamed the generic helpers, should we use the
writeback/invalidate/writeback & invalidate terminology here too?
I think it'd be nice to make the "driver" functions match the generic
implementations's names (even though that means not making the
instruction naming).
> The above function pointers are provided to be overridden for platforms
> needing CMO.
>
> Convert ZICBOM and T-HEAD CMO to use function pointers.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v6->v7
> * Updated commit description
> * Fixed build issues when CONFIG_ERRATA_THEAD_CMO=n
> * Used static const struct ptr to register CMO ops
> * Dropped riscv_dma_noncoherent_cmo_ops
> * Moved ZICBOM CMO setup to setup.c
Why'd you do that?
What is the reason that the Zicbom stuff cannot live in
dma-noncoherent.[ch] and only expose, say:
void riscv_cbom_register_cmo_ops(void)
{
riscv_noncoherent_register_cache_ops(&zicbom_cmo_ops);
}
which you then call from setup.c?
> v5->v6
> * New patch
> ---
> arch/riscv/errata/thead/errata.c | 76 ++++++++++++++++++++++++
> arch/riscv/include/asm/dma-noncoherent.h | 73 +++++++++++++++++++++++
> arch/riscv/include/asm/errata_list.h | 53 -----------------
> arch/riscv/kernel/setup.c | 49 ++++++++++++++-
> arch/riscv/mm/dma-noncoherent.c | 25 ++++++--
> arch/riscv/mm/pmem.c | 6 +-
> 6 files changed, 221 insertions(+), 61 deletions(-)
> create mode 100644 arch/riscv/include/asm/dma-noncoherent.h
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +
> +#define ZICBOM_CMO_OP(_op, _start, _size, _cachesize) \
> + asm volatile("mv a0, %1\n\t" \
> + "j 2f\n\t" \
> + "3:\n\t" \
> + CBO_##_op(a0) \
> + "add a0, a0, %0\n\t" \
> + "2:\n\t" \
> + "bltu a0, %2, 3b\n\t" \
> + : : "r"(_cachesize), \
> + "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
> + "r"((unsigned long)(_start) + (_size)) \
> + : "a0")
> +
> +static void zicbom_cmo_clean_range(unsigned long addr, unsigned long size)
> +{
> + ZICBOM_CMO_OP(clean, addr, size, riscv_cbom_block_size);
> +}
> +
> +static void zicbom_cmo_flush_range(unsigned long addr, unsigned long size)
> +{
> + ZICBOM_CMO_OP(flush, addr, size, riscv_cbom_block_size);
> +}
> +
> +static void zicbom_cmo_inval_range(unsigned long addr, unsigned long size)
> +{
> + ZICBOM_CMO_OP(inval, addr, size, riscv_cbom_block_size);
> +}
> +
> +const struct riscv_cache_ops zicbom_cmo_ops = {
> + .clean_range = &zicbom_cmo_clean_range,
> + .inv_range = &zicbom_cmo_inval_range,
> + .flush_range = &zicbom_cmo_flush_range,
> +};
> +
> +static void zicbom_register_cmo_ops(void)
> +{
> + riscv_noncoherent_register_cache_ops(&zicbom_cmo_ops);
> +}
> +#else
> +static void zicbom_register_cmo_ops(void) {}
> +#endif
I think all of the above should be prefixed with riscv_cbom to match the
other riscv_cbom stuff we already have.
Although, given the discussion elsewhere about just falling back to
zicbom in the absence of specific ops, most of these functions will
probably disappear (if not all of them).
Cheers,
Conor.
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next prev parent reply other threads:[~2023-03-31 12:25 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 20:42 [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Prabhakar
2023-03-30 20:42 ` [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-03-30 21:34 ` Arnd Bergmann
2023-03-31 7:54 ` Conor Dooley
2023-03-31 7:58 ` Arnd Bergmann
2023-03-31 10:37 ` Lad, Prabhakar
2023-03-31 10:44 ` Arnd Bergmann
2023-03-31 12:11 ` Lad, Prabhakar
2023-04-03 17:00 ` Lad, Prabhakar
2023-03-31 10:55 ` Conor Dooley
2023-03-31 11:36 ` Arnd Bergmann
2023-03-31 7:31 ` Geert Uytterhoeven
2023-03-31 10:45 ` Lad, Prabhakar
2023-03-31 12:24 ` Conor Dooley [this message]
2023-04-03 18:23 ` Lad, Prabhakar
2023-04-03 18:31 ` Conor Dooley
2023-04-04 5:29 ` Christoph Hellwig
2023-04-04 6:24 ` Biju Das
2023-04-04 15:42 ` Christoph Hellwig
2023-04-05 6:08 ` Biju Das
2023-04-07 0:03 ` Andrea Parri
2023-04-07 5:33 ` Christoph Hellwig
2023-04-04 6:50 ` Arnd Bergmann
2023-04-04 6:59 ` Conor Dooley
2023-04-06 18:59 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-03-30 20:42 ` [PATCH v7 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-03-30 20:42 ` [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-03-31 10:21 ` Conor Dooley
2023-03-31 10:47 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-03-31 12:45 ` Conor Dooley
2023-03-31 20:17 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-03-31 7:37 ` Geert Uytterhoeven
2023-03-31 7:37 ` Geert Uytterhoeven
2023-03-31 18:05 ` [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Conor Dooley
2023-03-31 20:09 ` Lad, Prabhakar
2023-03-31 20:15 ` Conor Dooley
2023-04-01 1:47 ` Icenowy Zheng
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