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AJvYcCUJxfN+lzfg+uOVajgmIoXwI15JTm2eszWEoSnFmSmZIBRgckjuTsjEwMVHx03bp0WslEunVa46jGaz@vger.kernel.org X-Gm-Message-State: AOJu0YzV6vTnBbox3xOpKl9QpmPnp5Jfe5xO9J2qQMH65mm0uYju8FG+ yh87jHog8yVwSbqQ5YU8HJp48TaRG0nn3dUiyYHgwOHLJv7lDKQ/U/L50t5z/YI= X-Gm-Gg: ASbGncsPEccMOjMqt/eoyk3a+UoPdr+A+TepcsU2gMr5Ox9J1qDnysLxuse4QKALLcc 2gdiVK2WxhLVFtIrpX6+1R7Hl5hhy8VDHt79FFlMuW8UH3Kg20fpNVC8j/VrAdRqpyKaEQ+i3vN DpJ5S4DEVqkuzV5upnWdQMhiW9d30IkoJcqx2BU1p/BQmVyH2RBfA3QvgCLjUb0ajfTluHqQiHE cAoAOMYrdZV+e1eOEimyxVBXsH9w7ogW1THuKDDOJCqI15Lq+Mod3E= X-Google-Smtp-Source: AGHT+IGJf7wL63WoRbY7Qyhb5Is/61MFEjb8kJtv26dX8E7BzS9uZFKdz8Zkaho5ks18oSvth2ZAng== X-Received: by 2002:a05:600c:3546:b0:431:5044:e388 with SMTP id 5b1f17b1804b1-434a9de78d0mr93513265e9.22.1732879474788; Fri, 29 Nov 2024 03:24:34 -0800 (PST) Received: from [10.1.1.109] ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa74f05asm80752145e9.1.2024.11.29.03.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 03:24:34 -0800 (PST) Message-ID: Subject: Re: [PATCH 4/6] arm64: dts: exynos: gs101: enable snps,dis_rxdet_inp3_quirk for DWC3 From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagan Sridharan , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org Date: Fri, 29 Nov 2024 11:24:32 +0000 In-Reply-To: <20241127-gs101-phy-lanes-orientation-dts-v1-4-5222d8508b71@linaro.org> References: <20241127-gs101-phy-lanes-orientation-dts-v1-0-5222d8508b71@linaro.org> <20241127-gs101-phy-lanes-orientation-dts-v1-4-5222d8508b71@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.1-4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-11-27 at 11:01 +0000, Andr=C3=A9 Draszik wrote: > This is required for the DWC3 core to reliably detect the connected > phy's Vbus state. >=20 > Signed-off-by: Andr=C3=A9 Draszik > --- > =C2=A0arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + > =C2=A01 file changed, 1 insertion(+) >=20 > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index 18d4e7852a1a..ab016fe9b99a 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -1302,6 +1302,7 @@ usbdrd31_dwc3: usb@0 { > =C2=A0 interrupts =3D IRQ_TYPE_LEVEL_HIGH 0>; > =C2=A0 phys =3D <&usbdrd31_phy 0>, <&usbdrd31_phy > 1>; > =C2=A0 phy-names =3D "usb2-phy", "usb3-phy"; > + snps,dis_rxdet_inp3_quirk; Seems this alone isn't enough in all cases, I'll send an update in a while. Cheers, Andre'