From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Rajendra Nayak <quic_rjendra@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@somainline.org, robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 3/4] soc: qcom: icc-bwmon: force clear counter/irq registers
Date: Thu, 1 Sep 2022 18:29:16 +0300 [thread overview]
Message-ID: <f16cbcaa-1457-b809-1323-39f07695bc7c@linaro.org> (raw)
In-Reply-To: <20220901124730.19460-4-quic_rjendra@quicinc.com>
On 01/09/2022 15:47, Rajendra Nayak wrote:
> In some SoCs we have to force clear the counter/irq clear registers as
> they are not self clearing after they are written into.
> sc7280 seems to be one such SoC, handle this with a quirk flag.
>
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-09-01 15:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 12:47 [PATCH 0/4] soc: qcom: icc-bwmon: Add support for llcc and cpu bwmon on sc7280 Rajendra Nayak
2022-09-01 12:47 ` [PATCH 1/4] dt-bindings: interconnect: qcom,msm8998-bwmon: Add support for sc7280 BWMONs Rajendra Nayak
2022-09-01 15:25 ` Krzysztof Kozlowski
2022-09-02 3:43 ` Rajendra Nayak
2022-09-01 12:47 ` [PATCH 2/4] soc: qcom: icc-bwmon: add support for sc7280 LLCC BWMON Rajendra Nayak
2022-09-01 15:27 ` Krzysztof Kozlowski
2022-09-02 4:04 ` Rajendra Nayak
2022-09-05 13:17 ` Krzysztof Kozlowski
2022-09-01 12:47 ` [PATCH 3/4] soc: qcom: icc-bwmon: force clear counter/irq registers Rajendra Nayak
2022-09-01 15:29 ` Krzysztof Kozlowski [this message]
2022-09-01 12:47 ` [PATCH 4/4] arm64: dts: qcom: sc7280: Add cpu and llcc BWMON Rajendra Nayak
2022-09-01 15:40 ` Krzysztof Kozlowski
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