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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Luo Jie <quic_luoj@quicinc.com>,
	agross@kernel.org, andersson@kernel.org, davem@davemloft.net,
	edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, andrew@lunn.ch, hkallweit1@gmail.com,
	linux@armlinux.org.uk, robert.marko@sartura.hr
Cc: linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	quic_srichara@quicinc.com
Subject: Re: [PATCH 4/9] net: mdio: ipq4019: configure CMN PLL clock for ipq5332
Date: Wed, 22 Nov 2023 21:24:24 +0100	[thread overview]
Message-ID: <f18b6552-bf8d-4826-969a-a0de60bd0ad3@linaro.org> (raw)
In-Reply-To: <20231115032515.4249-5-quic_luoj@quicinc.com>



On 11/15/23 04:25, Luo Jie wrote:
> The reference clock of CMN PLL block is selectable, the internal
> 48MHZ is used by default.
> 
> The output clock of CMN PLL block is for providing the clock
> source of ethernet device(such as qca8084), there are 1 X 25MHZ
> and 3 x 50MHZ output clocks available.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>   drivers/net/mdio/mdio-ipq4019.c | 81 ++++++++++++++++++++++++++++++++-
>   1 file changed, 80 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
> index 93ae4684de31..ca9cda98d1f8 100644
> --- a/drivers/net/mdio/mdio-ipq4019.c
> +++ b/drivers/net/mdio/mdio-ipq4019.c
> @@ -43,6 +43,13 @@
>   /* Maximum SOC PCS(uniphy) number on IPQ platform */
>   #define ETH_LDO_RDY_CNT				3
>   
> +#define CMN_PLL_REFERENCE_CLOCK			0x784
> +#define CMN_PLL_REFCLK_INDEX			GENMASK(3, 0)
> +#define CMN_PLL_REFCLK_EXTERNAL			BIT(9)
> +
> +#define CMN_PLL_POWER_ON_AND_RESET		0x780
> +#define CMN_ANA_EN_SW_RSTN			BIT(6)
> +
>   enum mdio_clk_id {
>   	MDIO_CLK_MDIO_AHB,
>   	MDIO_CLK_UNIPHY0_AHB,
> @@ -54,6 +61,7 @@ enum mdio_clk_id {
>   
>   struct ipq4019_mdio_data {
>   	void __iomem *membase;
> +	void __iomem *cmn_membase;
>   	void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT];
>   	struct clk *clk[MDIO_CLK_CNT];
>   	struct gpio_descs *reset_gpios;
> @@ -227,12 +235,73 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
>   	return 0;
>   }
>   
> +/* For the CMN PLL block, the reference clock can be configured according to
> + * the device tree property "cmn_ref_clk", the internal 48MHZ is used by default
> + * on the ipq533 platform.
> + *
> + * The output clock of CMN PLL block is provided to the MDIO slave devices,
> + * threre are 4 CMN PLL output clocks (1x25MHZ + 3x50MHZ) enabled by default.
> + *
> + * such as the output 50M clock for the qca8084 PHY.
> + */
> +static void ipq_cmn_clock_config(struct mii_bus *bus)
> +{
> +	u32 reg_val;
> +	const char *cmn_ref_clk;
> +	struct ipq4019_mdio_data *priv = bus->priv;
> +
> +	if (priv && priv->cmn_membase) {
> +		reg_val = readl(priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK);
> +		reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
> +
> +		/* Select reference clock source */
> +		cmn_ref_clk = of_get_property(bus->parent->of_node, "cmn_ref_clk", NULL);
> +		if (!cmn_ref_clk) {
> +			/* Internal 48MHZ selected by default */
> +			reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
> +		} else {
> +			if (!strcmp(cmn_ref_clk, "external_25MHz"))
As pointed out by others, such string properties won't go through

Konrad

  parent reply	other threads:[~2023-11-22 20:24 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-15  3:25 [PATCH 0/9] add MDIO changes on ipq5332 platform Luo Jie
2023-11-15  3:25 ` [PATCH 1/9] net: mdio: ipq4019: increase eth_ldo_rdy for " Luo Jie
2023-11-15 13:44   ` Andrew Lunn
2023-11-16  9:35     ` Jie Luo
2023-11-16 11:57   ` Krzysztof Kozlowski
2023-11-17  9:56     ` Jie Luo
2023-11-15  3:25 ` [PATCH 2/9] net: mdio: ipq4019: Enable the clocks " Luo Jie
2023-11-20 14:22   ` Konrad Dybcio
2023-11-21 10:28     ` Jie Luo
2023-11-21 14:04       ` Andrew Lunn
2023-11-23 11:02         ` Jie Luo
2023-11-27  9:37   ` Simon Horman
2023-11-28  7:07     ` Jie Luo
2023-11-15  3:25 ` [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset " Luo Jie
2023-11-15 15:11   ` Andrew Lunn
2023-11-16 11:13     ` Jie Luo
2023-11-16 11:19       ` Robert Marko
2023-11-16 11:29         ` Jie Luo
2023-11-16 17:20       ` Andrew Lunn
2023-11-17  9:59         ` Jie Luo
2023-12-04  8:53         ` Jie Luo
2023-11-15  3:25 ` [PATCH 4/9] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-11-15 15:19   ` Andrew Lunn
2023-11-16 10:48     ` Jie Luo
2023-11-22 20:24   ` Konrad Dybcio [this message]
2023-11-15  3:25 ` [PATCH 5/9] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-11-15 15:22   ` Andrew Lunn
2023-11-16 10:47     ` Jie Luo
2023-11-15  3:25 ` [PATCH 6/9] net: mdio: ipq4019: Support qca8084 switch register access Luo Jie
2023-11-15  3:25 ` [PATCH 7/9] net: mdio: ipq4019: program phy address when "fixup" defined Luo Jie
2023-11-15 16:17   ` Andrew Lunn
2023-11-16 11:17     ` Jie Luo
2023-11-15  3:25 ` [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations Luo Jie
2023-11-15 16:20   ` Andrew Lunn
2023-11-15 17:01     ` Konrad Dybcio
2023-11-15 17:03       ` Robert Marko
2023-11-16 10:45         ` Jie Luo
2023-11-16 17:08           ` Andrew Lunn
2023-11-17 10:05             ` Jie Luo
2023-11-16 10:44       ` Jie Luo
2023-11-16 10:47     ` Jie Luo
2023-11-16 17:12       ` Andrew Lunn
2023-11-17 10:15         ` Jie Luo
2023-11-15  3:25 ` [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-11-15  4:20   ` Rob Herring
2023-11-15 14:35   ` Andrew Lunn
2023-11-16 11:22     ` Jie Luo
2023-11-16 11:56   ` Krzysztof Kozlowski
2023-11-17 10:36     ` Jie Luo
2023-11-17 10:40       ` Krzysztof Kozlowski
2023-11-17 11:20         ` Jie Luo
2023-11-17 12:43           ` Krzysztof Kozlowski
2023-11-18  8:07             ` Jie Luo
2023-11-18 15:36               ` Andrew Lunn
2023-11-20  9:00                 ` Jie Luo

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