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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b003db012d49b7sm7025228wms.2.2023.01.19.03.33.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 03:33:42 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 11:33:40 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH] dt-bindings: clock: qcom,a53pll: drop operating-points-v2 Content-Language: en-US To: Krzysztof Kozlowski , Bjorn Andersson Cc: Stephen Boyd , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, fabien.parent@linaro.org References: <20230113145859.82868-1-krzysztof.kozlowski@linaro.org> <063c5516-417d-7c21-b58f-a6552779a621@linaro.org> <705c78c1d0da18089419b064832d5fed.sboyd@kernel.org> <20230119031136.27vson2awemt3nkt@builder.lan> <776b67b2-2405-36f5-f072-78f33ae59fcc@linaro.org> From: Bryan O'Donoghue In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/01/2023 11:04, Krzysztof Kozlowski wrote: > On 19/01/2023 11:55, Bryan O'Donoghue wrote: >> On 19/01/2023 03:11, Bjorn Andersson wrote: >>> On Wed, Jan 18, 2023 at 11:11:00AM -0800, Stephen Boyd wrote: >>>> Quoting Krzysztof Kozlowski (2023-01-15 06:35:23) >>>>> On 13/01/2023 21:28, Stephen Boyd wrote: >>>>>> Quoting Krzysztof Kozlowski (2023-01-13 06:58:59) >>>>>>> The CPU PLL clock node does not use OPP tables (neither driver). >>>>>> >>>>>> What device is qcom_a53pll_get_freq_tbl() operating on? >>>>> >>>>> On its own, internal table. While of course driver could be converted to >>>>> operating-points-v2, no one did it within last 5 years, so why it should >>>>> happen now? >>>>> >>>> >>>> The property was added mid 2021 by Shawn[1], that's not 5 years ago. I >>>> guess there were plans to add an OPP table that never happened[2]? Is >>>> Shawn still working on this? If not, we should revert the OPP code out >>>> of the driver. >>>> >>> >>> @Bryan, what do you think about this? >> >> I'd be in favour of starting the CPR patchset instead, which depends on >> the opps. >> >> I think @Fabien has been waiting on the core 8939 dtsi, I also think the >> dtsi is close enough to merge that we could reasonably initiate the CPR >> stuff. > > So you would make use of operating-points-v2 property? Then probably we > also miss opp-table, but anyway this patch can be dropped then. > > Best regards, > Krzysztof > Yep. Looks something like this. CPU2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; next-level-cache = <&L2_1>; enable-method = "qcom,kpss-acc-v2"; qcom,acc = <&acc2>; qcom,saw = <&saw2>; clocks = <&apcs1>; operating-points-v2 = <&cluster1_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; #cooling-cells = <2>; capacity-dmips-mhz = <1024>; }; cluster1_opp_table: cluster1-opp-table { compatible = "operating-points-v2-qcom-cpu"; opp-shared; /* Used by qcom-cpufreq-nvmem.c */ nvmem-cells = <&cpr_efuse_speedbin_pvs>; nvmem-cell-names = "cpr_efuse_speedbin_pvs"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-supported-hw = <0x3f>; required-opps = <&cpr_opp3>; }; opp-345600000 { opp-hz = /bits/ 64 <345600000>; opp-supported-hw = <0x3f>; required-opps = <&cpr_opp3>; }; }; cpr_opp_table: cpr-opp-table { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { opp-hz = /bits/ 64 <200000000>; opp-level = <1>; qcom,opp-fuse-level = <1>; }; cpr_opp2: opp2 { opp-hz = /bits/ 64 <345600000>; opp-level = <2>; qcom,opp-fuse-level = <1>; }; cpr_opp3: opp3 { opp-hz = /bits/ 64 <400000000>; opp-level = <3>; qcom,opp-fuse-level = <1>; }; }; /* etc */ }; --- bod