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Mon, 14 Oct 2024 10:41:28 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 941EC40050; Mon, 14 Oct 2024 10:39:59 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C17BF269E1E; Mon, 14 Oct 2024 10:38:41 +0200 (CEST) Received: from [10.252.14.29] (10.252.14.29) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 14 Oct 2024 10:38:40 +0200 Message-ID: Date: Mon, 14 Oct 2024 10:38:36 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] hwrng: stm32 - implement support for STM32MP25x platforms To: Marek Vasut , Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Lionel Debieve CC: , , , , References: <20241011-rng-mp25-v2-v2-0-76fd6170280c@foss.st.com> <20241011-rng-mp25-v2-v2-2-76fd6170280c@foss.st.com> <318dbd5e-f547-4d78-b42e-4dcacc08d328@denx.de> Content-Language: en-US From: Gatien CHEVALLIER In-Reply-To: <318dbd5e-f547-4d78-b42e-4dcacc08d328@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 On 10/11/24 18:17, Marek Vasut wrote: > On 10/11/24 5:41 PM, Gatien Chevallier wrote: > > [...] > >> @@ -551,6 +565,41 @@ static int stm32_rng_probe(struct platform_device >> *ofdev) >>       priv->rng.read = stm32_rng_read; >>       priv->rng.quality = 900; >> +    if (!priv->data->nb_clock || priv->data->nb_clock > 2) >> +        return -EINVAL; >> + >> +    priv->clk_bulk = devm_kzalloc(dev, priv->data->nb_clock * >> sizeof(*priv->clk_bulk), >> +                      GFP_KERNEL); >> +    if (!priv->clk_bulk) >> +        return -ENOMEM; > > Try this: > > ret = devm_clk_bulk_get(dev, priv->data->nb_clock, priv->clk_bulk); > ... > // Swap the clock if they are not in the right order: > if (priv->data->nb_clock == 2 && >     strcmp(__clk_get_name(priv->clk_bulk[0].clk), "core")) > { >  const char *id = priv->clk_bulk[1].id; >  struct clk *clk = priv->clk_bulk[1].clk; >  priv->clk_bulk[1].id = priv->clk_bulk[0].id; >  priv->clk_bulk[1].clk = priv->clk_bulk[0].clk; >  priv->clk_bulk[0].id = id; >  priv->clk_bulk[0].clk = clk; > } > Hi Marek, This won't work as the name returned by this API is clk->core->name. AFAICT, it doesn't correspond to the names present in the device tree under the "clock-names" property. Any other idea or are you fine with what's below? Thanks, Gatien >> +    if (priv->data->nb_clock == 2) { >> +        struct clk *clk; >> +        struct clk *bus_clk; >> + >> +        clk = devm_clk_get(&ofdev->dev, "core"); >> +        if (IS_ERR(clk)) >> +            return PTR_ERR(clk); >> + >> +        bus_clk = devm_clk_get(&ofdev->dev, "bus"); >> +        if (IS_ERR(clk)) >> +            return PTR_ERR(bus_clk); >> + >> +        priv->clk_bulk[0].clk = clk; >> +        priv->clk_bulk[0].id = "core"; >> +        priv->clk_bulk[1].clk = bus_clk; >> +        priv->clk_bulk[1].id = "bus"; >> +    } else { >> +        struct clk *clk; >> + >> +        clk = devm_clk_get(&ofdev->dev, NULL); >> +        if (IS_ERR(clk)) >> +            return PTR_ERR(clk); >> + >> +        priv->clk_bulk[0].clk = clk; >> +        priv->clk_bulk[0].id = "core"; >> +    } >