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Sun, 08 Mar 2026 11:20:18 -0700 (PDT) Message-ID: Date: Sun, 8 Mar 2026 13:20:17 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] riscv: cpufeature: Add ISA extension parsing for Supm To: Guodong Xu Cc: Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heinrich Schuchardt , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Evan Green , Andrew Jones , Conor Dooley References: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> <20260125-supm-ext-id-v2-2-1e3b9714c860@riscstar.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20260125-supm-ext-id-v2-2-1e3b9714c860@riscstar.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Guodong, On 2026-01-24 7:36 PM, Guodong Xu wrote: > Supm has been ratified in the RISC-V Pointer Masking specification > (Version 1.0, 10/2024) and is mandated in RVA23 Profiles (Version 1.0, > 2024-10-17) for RVA23U64. Supm indicates userspace pointer masking > support. > > Remove the previous macro aliasing of Supm to Ssnpm/Smnpm in hwcap.h, > treating Supm as a distinct RISC-V ISA extension ID. > > Add ISA parsing logic for Supm, and implement a validator to ensure > that Supm is only reported as available if Kconfig allows it and the > underlying Ssnpm (for supervisor mode) or Smnpm (for machine mode) > extension is present. Supm relies on Ssnpm or Smnpm to provide the > underlying hardware implementation. > > With this change, "supm" will be reported (when available) in > /proc/cpuinfo as part of the "isa" and "hart isa" string. > > Reviewed-by: Conor Dooley > Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/#r [1] > Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifive.com/#r [2] > Signed-off-by: Guodong Xu > --- > v2: Add Reviewed-by from Conor. > Update RISCV_ISA_EXT_SUPM id to solve rebase conflict. > --- > arch/riscv/include/asm/hwcap.h | 3 +-- > arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++++++++++++++++++-- > 2 files changed, 34 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 7ef8e5f55c8d..aa2af21f3bd3 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -112,6 +112,7 @@ > #define RISCV_ISA_EXT_ZCLSD 103 > #define RISCV_ISA_EXT_ZICFILP 104 > #define RISCV_ISA_EXT_ZICFISS 105 > +#define RISCV_ISA_EXT_SUPM 106 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > @@ -120,10 +121,8 @@ > > #ifdef CONFIG_RISCV_M_MODE > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > -#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM > #else > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > -#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM > #endif > > #endif /* _ASM_RISCV_HWCAP_H */ > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1734f9a4c2fd..e1f7ad882289 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -317,6 +317,27 @@ static int riscv_cfiss_validate(const struct riscv_isa_ext_data *data, > return 0; > } > > +static int riscv_ext_supm_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (!IS_ENABLED(CONFIG_RISCV_ISA_SUPM)) > + return -EINVAL; > + > + /* > + * Supm requires Ssnpm for S-mode or Smnpm for M-mode to provide > + * pointer masking for the U-mode execution environment. > + */ > + if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SMNPM)) > + return 0; > + } else { > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSNPM)) > + return 0; > + } > + > + return -EPROBE_DEFER; > +} > + > static const unsigned int riscv_a_exts[] = { > RISCV_ISA_EXT_ZAAMO, > RISCV_ISA_EXT_ZALRSC, > @@ -450,6 +471,15 @@ static const unsigned int riscv_c_exts[] = { > RISCV_ISA_EXT_ZCD, > }; > > +/* > + * Smnpm and Ssnpm provide pointer masking for the next lower privilege mode > + * (U-mode), thus enabling Supm. Both extensions imply the same subset. If Linux is running in S-mode, then Smnpm does _not_ imply Supm. So this list cannot be shared between Ssnpm and Smnpm. (When running Linux in M-mode, I think we assume S-mode isn't supported, so the opposite case isn't possible. If you do run M-mode Linux on M/S/U hardware, I think there are other things that explode spectacularly, since we will touch for example the wrong envcfg register.) > + */ > +static const unsigned int riscv_supm_exts[] = { > + RISCV_ISA_EXT_XLINUXENVCFG, > + RISCV_ISA_EXT_SUPM > +}; > + > /* > * The canonical order of ISA extension names in the ISA string is defined in > * chapter 27 of the unprivileged specification. > @@ -577,12 +607,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), > - __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), > + __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > - __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), > + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > + __RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_validate), I don't think this quite matches what we want either. We don't want to accept Supm from the devicetree at all, so it shouldn't be in this array (just like Xlinuxenvcfg is not in this array). You'll need new code in riscv_resolve_isa() (or its callers) to set the RISCV_ISA_EXT_SUPM bit under the right conditions. Regards, Samuel > __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), > __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate), > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), >