From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v1 2/3] clk: starfive: Add StarFive JH7110 PLL clock driver
Date: Thu, 23 Feb 2023 18:03:47 +0800 [thread overview]
Message-ID: <f23b3755-e2dd-f858-02ad-3f1b58934bc6@starfivetech.com> (raw)
In-Reply-To: <50b6fb73-afb2-051b-7969-d7fbbe1e6175@linaro.org>
On 2023/2/23 17:35, Krzysztof Kozlowski wrote:
> On 23/02/2023 10:32, Xingyu Wu wrote:
>> On 2023/2/23 16:56, Krzysztof Kozlowski wrote:
>>> On 21/02/2023 15:11, Xingyu Wu wrote:
>>>> Add driver for the StarFive JH7110 PLL clock controller and
>>>> modify the JH7110 system clock driver to rely on this PLL clocks.
>>>>
>>>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>>>> ---
>>>
>>>
>>>> +
>>>> +static int jh7110_pll_clk_probe(struct platform_device *pdev)
>>>> +{
>>>> + int ret;
>>>> + struct of_phandle_args args;
>>>> + struct regmap *pll_syscon_regmap;
>>>> + unsigned int idx;
>>>> + struct jh7110_clk_pll_priv *priv;
>>>> + struct jh7110_clk_pll_data *data;
>>>> + char *pll_name[JH7110_PLLCLK_END] = {
>>>> + "pll0_out",
>>>> + "pll1_out",
>>>> + "pll2_out"
>>>> + };
>>>> +
>>>> + priv = devm_kzalloc(&pdev->dev,
>>>> + struct_size(priv, data, JH7110_PLLCLK_END),
>>>> + GFP_KERNEL);
>>>> + if (!priv)
>>>> + return -ENOMEM;
>>>> +
>>>> + priv->dev = &pdev->dev;
>>>> + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "starfive,sysreg", 0, 0, &args);
>>>
>>> 1. Wrong wrapping. Wrap code at 80 as coding style asks.
>>>
>>> 2. Why you are using syscon for normal, device MMIO operation? Your DTS
>>> also points that this is incorrect, hacky representation of hardware.
>>> Don't add devices to DT to fake places and then overuse syscon to fix
>>> that fake placement. The clock is in system registers, thus it must be
>>> there.
>>>
>>> 3. Even if this stays, why so complicated code instead of
>>> syscon_regmap_lookup_by_phandle()?
>>>
>>
>> Thanks for your advice. Will use syscon_regmap_lookup_by_phandle instead it
>> and remove useless part.
>
> So you ignored entirely part 2? This was the main comment... I am going
> to keep NAK-ing it then.
What I understand to mean is that I cannot use a fake node to operate syscon
registers. So I should move the PLL node under syscon node directly. Is it ok?
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-02-23 10:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 14:11 [PATCH v1 0/3] Add PLL clocks driver for StarFive JH7110 Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 1/3] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-02-22 9:11 ` Krzysztof Kozlowski
2023-02-23 8:34 ` Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 2/3] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-02-23 8:56 ` Krzysztof Kozlowski
2023-02-23 9:32 ` Xingyu Wu
2023-02-23 9:35 ` Krzysztof Kozlowski
2023-02-23 10:03 ` Xingyu Wu [this message]
2023-02-23 10:10 ` Krzysztof Kozlowski
2023-02-24 7:45 ` Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node Xingyu Wu
2023-02-22 9:09 ` Krzysztof Kozlowski
2023-02-23 8:47 ` Xingyu Wu
2023-02-23 8:52 ` Krzysztof Kozlowski
2023-02-23 9:03 ` Xingyu Wu
2023-02-23 9:04 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f23b3755-e2dd-f858-02ad-3f1b58934bc6@starfivetech.com \
--to=xingyu.wu@starfivetech.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=hal.feng@starfivetech.com \
--cc=kernel@esmil.dk \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).