[PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns

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* [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram
@ 2022-02-22 11:39 Hari Prasath
  2022-02-22 11:39 ` [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5 Hari Prasath
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Hari Prasath @ 2022-02-22 11:39 UTC (permalink / raw)
  To: nicolas.ferre, claudiu.beznea, davem, alexandre.belloni,
	ludovic.desroches, robh+dt, linux-arm-kernel, devicetree,
	linux-kernel, linux
  Cc: Hari.PrasathGE

Limit the size of SRAM available for the rest of kernel via genalloc API's to
13k. The rest of the SRAM is used by CAN controllers and hence this restriction.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index eddcfbf4d223..6c7012f74b10 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -65,7 +65,7 @@
 		compatible = "mmio-sram";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		reg = <0x100000 0x20000>;
+		reg = <0x100000 0x3400>;
 		ranges;
 	};
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5
  2022-02-22 11:39 [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Hari Prasath
@ 2022-02-22 11:39 ` Hari Prasath
  2022-02-22 11:39 ` [PATCH] 3/3] ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek Hari Prasath
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 7+ messages in thread
From: Hari Prasath @ 2022-02-22 11:39 UTC (permalink / raw)
  To: nicolas.ferre, claudiu.beznea, davem, alexandre.belloni,
	ludovic.desroches, robh+dt, linux-arm-kernel, devicetree,
	linux-kernel, linux
  Cc: Hari.PrasathGE

Add support for all the six CAN controllers of sama7g5.The internal SRAM of 128KB
is split among the CAN controllers for the message RAM elements leaving a small
portion reserved for power management. The SRAM split up is as below.

Lower 64K:
        PM       13K
        can-0    17K
        can-1    17K
        can-2    17K

Higher 64K:

        can-3    17K
        can-4    17K
        can-5    17K

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 96 ++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6c7012f74b10..d4d87db8e212 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -211,6 +211,102 @@
 			status = "disabled";
 		};
 
+		can0: can@e0828000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0828000 0x100>, <0x100000 0x7800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can1: can@e082c000 {
+			compatible = "bosch,m_can";
+			reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can2: can@e0830000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0830000 0x100>, <0x100000 0x10000>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can3: can@e0834000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0834000 0x100>, <0x110000 0x4400>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can4: can@e0838000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0838000 0x100>, <0x110000 0x8800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can5: can@e083c000 {
+			compatible = "bosch,m_can";
+			reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+			assigned-clock-rates = <40000000>;
+			bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
 		adc: adc@e1000000 {
 			compatible = "microchip,sama7g5-adc";
 			reg = <0xe1000000 0x200>;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH] 3/3] ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek
  2022-02-22 11:39 [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Hari Prasath
  2022-02-22 11:39 ` [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5 Hari Prasath
@ 2022-02-22 11:39 ` Hari Prasath
  2022-02-22 20:46 ` [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Alexandre Belloni
  2022-02-24 15:50 ` Nicolas Ferre
  3 siblings, 0 replies; 7+ messages in thread
From: Hari Prasath @ 2022-02-22 11:39 UTC (permalink / raw)
  To: nicolas.ferre, claudiu.beznea, davem, alexandre.belloni,
	ludovic.desroches, robh+dt, linux-arm-kernel, devicetree,
	linux-kernel, linux
  Cc: Hari.PrasathGE

Enable the can0 and can1 controllers in sama7g5-ek board along with
its pin mux settings.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
---
 arch/arm/boot/dts/at91-sama7g5ek.dts | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index ccf9e224da78..5211a8c9a19c 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -131,6 +131,18 @@
 	status = "okay";
 };
 
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_default>;
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_default>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vddcpu>;
 };
@@ -454,6 +466,19 @@
 };
 
 &pioA {
+
+	pinctrl_can0_default: can0_default {
+		pinmux = <PIN_PD12__CANTX0>,
+			 <PIN_PD13__CANRX0 >;
+		bias-disable;
+	};
+
+	pinctrl_can1_default: can1_default {
+		pinmux = <PIN_PD14__CANTX1>,
+			 <PIN_PD15__CANRX1 >;
+		bias-disable;
+	};
+
 	pinctrl_flx0_default: flx0_default {
 		pinmux = <PIN_PE3__FLEXCOM0_IO0>,
 			 <PIN_PE4__FLEXCOM0_IO1>,
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram
  2022-02-22 11:39 [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Hari Prasath
  2022-02-22 11:39 ` [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5 Hari Prasath
  2022-02-22 11:39 ` [PATCH] 3/3] ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek Hari Prasath
@ 2022-02-22 20:46 ` Alexandre Belloni
  2022-02-24 15:47   ` Nicolas Ferre
  2022-02-24 15:50 ` Nicolas Ferre
  3 siblings, 1 reply; 7+ messages in thread
From: Alexandre Belloni @ 2022-02-22 20:46 UTC (permalink / raw)
  To: Hari Prasath
  Cc: nicolas.ferre, claudiu.beznea, davem, ludovic.desroches, robh+dt,
	linux-arm-kernel, devicetree, linux-kernel, linux

On 22/02/2022 17:09:22+0530, Hari Prasath wrote:
> Limit the size of SRAM available for the rest of kernel via genalloc API's to
> 13k. The rest of the SRAM is used by CAN controllers and hence this restriction.
> 

Certainly not, if the can controller need the SRAM, they have to
allocate it properly.

> Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
> ---
>  arch/arm/boot/dts/sama7g5.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index eddcfbf4d223..6c7012f74b10 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -65,7 +65,7 @@
>  		compatible = "mmio-sram";
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> -		reg = <0x100000 0x20000>;
> +		reg = <0x100000 0x3400>;
>  		ranges;
>  	};
>  
> -- 
> 2.17.1
> 

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram
  2022-02-22 20:46 ` [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Alexandre Belloni
@ 2022-02-24 15:47   ` Nicolas Ferre
  2022-02-24 17:50     ` Alexandre Belloni
  0 siblings, 1 reply; 7+ messages in thread
From: Nicolas Ferre @ 2022-02-24 15:47 UTC (permalink / raw)
  To: Alexandre Belloni, Hari Prasath
  Cc: claudiu.beznea, davem, ludovic.desroches, robh+dt,
	linux-arm-kernel, devicetree, linux-kernel, linux

On 22/02/2022 at 21:46, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 22/02/2022 17:09:22+0530, Hari Prasath wrote:
>> Limit the size of SRAM available for the rest of kernel via genalloc API's to
>> 13k. The rest of the SRAM is used by CAN controllers and hence this restriction.
>>
> 
> Certainly not, if the can controller need the SRAM, they have to
> allocate it properly.

I'm not sure that bosh mcan driver can be used with dynamic allocation 
of SRAM. Is it what you're thinking about?

In the meantime, I'm taking the CAN patches of this series as they match 
what we currently do for other users of mcan driver on other SoCs.

Regards,
   Nicolas

>> Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
>> ---
>>   arch/arm/boot/dts/sama7g5.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
>> index eddcfbf4d223..6c7012f74b10 100644
>> --- a/arch/arm/boot/dts/sama7g5.dtsi
>> +++ b/arch/arm/boot/dts/sama7g5.dtsi
>> @@ -65,7 +65,7 @@
>>                compatible = "mmio-sram";
>>                #address-cells = <1>;
>>                #size-cells = <1>;
>> -             reg = <0x100000 0x20000>;
>> +             reg = <0x100000 0x3400>;
>>                ranges;
>>        };
>>
>> --
>> 2.17.1
>>
> 
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com


-- 
Nicolas Ferre

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram
  2022-02-24 15:47   ` Nicolas Ferre
@ 2022-02-24 17:50     ` Alexandre Belloni
  0 siblings, 0 replies; 7+ messages in thread
From: Alexandre Belloni @ 2022-02-24 17:50 UTC (permalink / raw)
  To: Nicolas Ferre
  Cc: Hari Prasath, claudiu.beznea, davem, ludovic.desroches, robh+dt,
	linux-arm-kernel, devicetree, linux-kernel, linux

On 24/02/2022 16:47:03+0100, Nicolas Ferre wrote:
> On 22/02/2022 at 21:46, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 22/02/2022 17:09:22+0530, Hari Prasath wrote:
> > > Limit the size of SRAM available for the rest of kernel via genalloc API's to
> > > 13k. The rest of the SRAM is used by CAN controllers and hence this restriction.
> > > 
> > 
> > Certainly not, if the can controller need the SRAM, they have to
> > allocate it properly.
> 
> I'm not sure that bosh mcan driver can be used with dynamic allocation of
> SRAM. Is it what you're thinking about?
> 

Yes, simply add a new compatible and do the allocation where necessary.
IT would be just like how we have different compatible strings for every
different macb integrations.


-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram
  2022-02-22 11:39 [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Hari Prasath
                   ` (2 preceding siblings ...)
  2022-02-22 20:46 ` [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Alexandre Belloni
@ 2022-02-24 15:50 ` Nicolas Ferre
  3 siblings, 0 replies; 7+ messages in thread
From: Nicolas Ferre @ 2022-02-24 15:50 UTC (permalink / raw)
  To: Hari Prasath, claudiu.beznea, davem, alexandre.belloni,
	ludovic.desroches, robh+dt, linux-arm-kernel, devicetree,
	linux-kernel, linux

On 22/02/2022 at 12:39, Hari Prasath wrote:
> Limit the size of SRAM available for the rest of kernel via genalloc API's to
> 13k. The rest of the SRAM is used by CAN controllers and hence this restriction.
> 
> Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Patches 2-3 taken for 5.18.

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/sama7g5.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index eddcfbf4d223..6c7012f74b10 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -65,7 +65,7 @@
>   		compatible = "mmio-sram";
>   		#address-cells = <1>;
>   		#size-cells = <1>;
> -		reg = <0x100000 0x20000>;
> +		reg = <0x100000 0x3400>;
>   		ranges;
>   	};
>   


-- 
Nicolas Ferre

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2022-02-24 17:50 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2022-02-22 11:39 ` [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5 Hari Prasath
2022-02-22 11:39 ` [PATCH] 3/3] ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek Hari Prasath
2022-02-22 20:46 ` [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Alexandre Belloni
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