From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D8AE4B5AE; Tue, 17 Sep 2024 17:45:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726595105; cv=none; b=fQopsNZMU6aXdgkS1mxlDt+cS9w0RxObfQg63Ba4mUrFFemOimaJkuQD9l0asPhtoFyLBmakb9cAdV9ZLZDiB7ChEwVWrE8MYjpBhUBQNtXifJzjgphVJh9ISKyfu15/XpuG//GHyv8UO2ic9ZAWXRYu60iyl9MmBOCA/fImSgw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726595105; c=relaxed/simple; bh=Xp6ZAq9hsiTKRria2h5DeY+qKHFXNOswbSuyjAmT2hw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=i/pEMxLyH4/omYmyqowuuOMPqmTAWTJYuF7xkQFWQyNMMgkB7EMvCKBTYKOJpcDKD7IGrgB1t6xM1zmPz/lf6YW4a0cfqru4xIDhNHCDYn96ptp+THQdN+qc+m4IYktawypCUGsRbyHWRT2xxKKHpiQ4NM78b9+FgG65fBagVp0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ECH2i6Eb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ECH2i6Eb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 272C0C4CEC5; Tue, 17 Sep 2024 17:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726595104; bh=Xp6ZAq9hsiTKRria2h5DeY+qKHFXNOswbSuyjAmT2hw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ECH2i6EbA/cdbPJIZ1ej2qvVLWFe91xElbs8DA8EGO2UStj1Ca8bpJ0hELsGWRhLp nal15XCSfUvXZ7LAiYjT7t1VqO7jQEIiSO3sueHG5lnj1FyRaI7lgedXPXPjhsYsyt rihJSSoOhrdr+V2G0wJyiWzzI9+8L/W5sbAsZfDbEZjV1ZcjSi2RWKjMYXRWR7ImT6 DI2k/PQqV9sPL2xI8AE1sEGRxgFt0J0cHDDY6NDzURhAMY/BgLa0UqgjfIBpuyIDhj bjWr5B1gDeK6UcpfiYFZmqN+Ja8lGgPF/Gw1aipNevKm8/JaWdf84H0qEzcIMy23IU cXvpgX6HufzQg== Message-ID: Date: Tue, 17 Sep 2024 19:44:58 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux To: Ciprian Costea , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , Radu Pirea References: <20240830113347.4048370-1-ciprianmarian.costea@oss.nxp.com> <20240830113347.4048370-2-ciprianmarian.costea@oss.nxp.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 30/08/2024 13:33, Ciprian Costea wrote: > From: Ciprian Marian Costea > > Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable > higher speed modes for SD (SDR50, DDR50, SDR104) and > eMMC (such as HS200, HS400/HS400ES). > > Signed-off-by: Radu Pirea > Signed-off-by: Ciprian Marian Costea > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ > .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + > .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + > arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ > .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + > 5 files changed, 318 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fa054bfe7d5c..7be430b78c83 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -162,6 +162,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { Are you sure that this passes dtbs_check W=1? Best regards, Krzysztof