[PATCH v3 0/3] Support ExynosAutov920 ufs phy driver

[PATCH v3 0/3] Support ExynosAutov920 ufs phy driver

[Sowon Na]

This patchset introduces ExynosAuto v920 SoC ufs phy driver as
Generic PHY driver framework.

Changes from v2:
- simplify function name from samsung_exynosautov920_ufs_phy_wait_cdr_lock
  to exynosautov920_ufs_phy_wait_cdr_lock
- return immediately after getting the CDR lock
- add comment for wait CDR lock

Changes from v1:
- use exynosautov920 instead of exynosauto to specify
- remove obvious comment
- change soc name as ExynosAutov920 to keep consistent
- use macros instead of magic numbers
- specify function name
- add error handling for CDR lock failure

Sowon Na (3):
  dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
  phy: samsung-ufs: support ExynosAutov920 ufs phy driver
  arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC

 .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |  11 ++
 drivers/phy/samsung/Makefile                  |   1 +
 drivers/phy/samsung/phy-exynosautov920-ufs.c  | 167 ++++++++++++++++++
 drivers/phy/samsung/phy-samsung-ufs.c         |   9 +-
 drivers/phy/samsung/phy-samsung-ufs.h         |   4 +
 6 files changed, 190 insertions(+), 3 deletions(-)
 create mode 100644 drivers/phy/samsung/phy-exynosautov920-ufs.c

-- 
2.45.2

[PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[Sowon Na]

Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f402e31bf58d..d70ffeb6e824 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -18,6 +18,7 @@ properties:
       - google,gs101-ufs-phy
       - samsung,exynos7-ufs-phy
       - samsung,exynosautov9-ufs-phy
+      - samsung,exynosautov920-ufs-phy
       - tesla,fsd-ufs-phy
 
   reg:
-- 
2.45.2

[PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs phy driver

[Sowon Na]

Add support for ExynosAutov920 ufs phy driver.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 drivers/phy/samsung/Makefile                 |   1 +
 drivers/phy/samsung/phy-exynosautov920-ufs.c | 167 +++++++++++++++++++
 drivers/phy/samsung/phy-samsung-ufs.c        |   9 +-
 drivers/phy/samsung/phy-samsung-ufs.h        |   4 +
 4 files changed, 178 insertions(+), 3 deletions(-)
 create mode 100644 drivers/phy/samsung/phy-exynosautov920-ufs.c

diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index fea1f96d0e43..342682638a87 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -7,6 +7,7 @@ phy-exynos-ufs-y			+= phy-gs101-ufs.o
 phy-exynos-ufs-y			+= phy-samsung-ufs.o
 phy-exynos-ufs-y			+= phy-exynos7-ufs.o
 phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
+phy-exynos-ufs-y			+= phy-exynosautov920-ufs.o
 phy-exynos-ufs-y			+= phy-fsd-ufs.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
 phy-exynos-usb2-y			+= phy-samsung-usb2.o
diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c b/drivers/phy/samsung/phy-exynosautov920-ufs.c
new file mode 100644
index 000000000000..8a7ba159bbfe
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for Samsung ExynosAuto v920 SoC
+ *
+ * Copyright (C) 2024 Samsung Electronics Co., Ltd.
+ */
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL			0x708
+#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK		0x1
+#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
+#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
+
+#define EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xCE4
+
+#define PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
+#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
+	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
+	PHY_COMN_REG_CFG(0x29, 0x22, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x04, 0x95, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x06, 0x30, PWR_MODE_ANY),
+
+	PHY_TRSV_REG_CFG_AUTOV920(0x200, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x201, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0A, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0C, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2E1, 0xC0, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x22D, 0xF8, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x234, 0x60, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x238, 0x13, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x239, 0x48, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23A, 0x01, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23B, 0x29, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23C, 0x2A, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23D, 0x01, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23E, 0x14, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x23F, 0x13, PWR_MODE_ANY),
+
+	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4A, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x25D, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x25E, 0x3F, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x25F, 0xFF, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x26F, 0xF0, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x273, 0x33, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x274, 0x50, PWR_MODE_ANY),
+
+	PHY_TRSV_REG_CFG_AUTOV920(0x284, 0x02, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x285, 0x02, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2A2, 0x04, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x27D, 0x01, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2FA, 0x01, PWR_MODE_ANY),
+
+	PHY_TRSV_REG_CFG_AUTOV920(0x286, 0x03, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x287, 0x03, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x288, 0x03, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x289, 0x03, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2B3, 0x04, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2B6, 0x0B, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2B7, 0x0B, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2B8, 0x0B, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2B9, 0x0B, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2BA, 0x0B, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2BB, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2BC, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2BD, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2BE, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x34B, 0x01, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x34C, 0x24, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x34D, 0x23, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x34E, 0x45, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x34F, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x350, 0x31, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x351, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x352, 0x02, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x353, 0x00, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x354, 0x01, PWR_MODE_ANY),
+
+	PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
+
+	END_UFS_PHY_CFG,
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {
+	PHY_TRSV_REG_CFG_AUTOV920(0x369, 0x11, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x03, PWR_MODE_ANY),
+
+	END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG,
+};
+
+#define DELAY_IN_US	40
+#define RETRY_CNT	100
+#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8
+int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
+{
+	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+	u32 reg, i;
+
+	struct samsung_ufs_phy_cfg cfg[4] = {
+		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
+		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
+		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
+		END_UFS_PHY_CFG,
+	};
+
+	for (i = 0; i < RETRY_CNT; i++) {
+		udelay(DELAY_IN_US);
+
+		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
+			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
+
+		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
+					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
+			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
+			return 0;
+		}
+
+		udelay(DELAY_IN_US);
+
+		/* Disable and enable CDR */
+		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
+		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
+	}
+
+	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
+	return -ETIMEDOUT;
+}
+
+static const struct samsung_ufs_phy_cfg *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {
+	[CFG_PRE_INIT]          = exynosautov920_pre_init_cfg,
+	[CFG_PRE_PWR_HS]        = exynosautov920_pre_pwr_hs_cfg,
+	[CFG_POST_PWR_HS]       = exynosautov920_post_pwr_hs_cfg,
+};
+
+static const char * const exynosautov920_ufs_phy_clks[] = {
+	"ref_clk",
+};
+
+const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
+	.cfgs = exynosautov920_ufs_phy_cfgs,
+	.isol = {
+		.offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL,
+		.mask = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK,
+		.en = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN,
+	},
+	.clk_list = exynosautov920_ufs_phy_clks,
+	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
+	.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
+};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 6c5d41552649..c13fe149bc75 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -28,9 +28,9 @@
 
 #define PHY_DEF_LANE_CNT	1
 
-static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
-				   const struct samsung_ufs_phy_cfg *cfg,
-				   u8 lane)
+void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
+			    const struct samsung_ufs_phy_cfg *cfg,
+			    u8 lane)
 {
 	enum {LANE_0, LANE_1}; /* lane index */
 
@@ -323,6 +323,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov9-ufs-phy",
 		.data = &exynosautov9_ufs_phy,
+	}, {
+		.compatible = "samsung,exynosautov920-ufs-phy",
+		.data = &exynosautov920_ufs_phy,
 	}, {
 		.compatible = "tesla,fsd-ufs-phy",
 		.data = &fsd_ufs_phy,
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 9b7deef6e10f..a28f148081d1 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -143,9 +143,13 @@ static inline void samsung_ufs_phy_ctrl_isol(
 }
 
 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
+int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
+void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
+			    const struct samsung_ufs_phy_cfg *cfg, u8 lane);
 
 extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;
 
-- 
2.45.2

[PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC

[Sowon Na]

Add UFS Phy for ExynosAutov920

Like ExynosAutov9, this also uses fixed-rate clock nodes until clock driver
has been supported. The clock nodes are initialized on bootloader stage
thus we don't need to control them so far.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index c759134c909e..505ba04722de 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -361,6 +361,17 @@ pinctrl_aud: pinctrl@1a460000 {
 			compatible = "samsung,exynosautov920-pinctrl";
 			reg = <0x1a460000 0x10000>;
 		};
+
+		ufs_0_phy: phy@16e04000 {
+			compatible = "samsung,exynosautov920-ufs-phy";
+			reg = <0x16e04000 0x4000>;
+			reg-names = "phy-pma";
+			clocks = <&xtcxo>;
+			clock-names = "ref_clk";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
 	};
 
 	timer {
-- 
2.45.2

RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[Alim Akhtar]

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Monday, November 18, 2024 7:40 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com; Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org>
> Subject: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> bindings
> 
> Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
I am not sure how we can help you, you are keep missing to collect all the tags
https://lkml.org/lkml/2024/11/7/617

>  Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> index f402e31bf58d..d70ffeb6e824 100644
> --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> @@ -18,6 +18,7 @@ properties:
>        - google,gs101-ufs-phy
>        - samsung,exynos7-ufs-phy
>        - samsung,exynosautov9-ufs-phy
> +      - samsung,exynosautov920-ufs-phy
>        - tesla,fsd-ufs-phy
> 
>    reg:
> --
> 2.45.2

RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[나소원/SOWON NA]

Hi Alim,

On 11/19/24 2:21 PM, Alim Akhtar wrote:
> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Tuesday, November 19, 2024 2:21 PM
> To: 'Sowon Na' <sowon.na@samsung.com>; robh@kernel.org; krzk@kernel.org;
> conor+dt@kernel.org; vkoul@kernel.org; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org; 'Krzysztof
> Kozlowski' <krzysztof.kozlowski@linaro.org>
> Subject: RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> bindings
> 
> 
> 
> > -----Original Message-----
> > From: Sowon Na <sowon.na@samsung.com>
> > Sent: Monday, November 18, 2024 7:40 AM
> > To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> > vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > sowon.na@samsung.com; Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org>
> > Subject: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> > bindings
> >
> > Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.
> >
> > Signed-off-by: Sowon Na <sowon.na@samsung.com>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > ---
> I am not sure how we can help you, you are keep missing to collect all the
> tags
> https://lkml.org/lkml/2024/11/7/617
> 
Really sorry for missing tags. I append it immediately, and will not miss anymore.
Your review helps me a lot and makes my patch better. I applied all your reviews to my patches.

Thank you a lot once again for your help.

> >  Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > index f402e31bf58d..d70ffeb6e824 100644
> > --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > @@ -18,6 +18,7 @@ properties:
> >        - google,gs101-ufs-phy
> >        - samsung,exynos7-ufs-phy
> >        - samsung,exynosautov9-ufs-phy
> > +      - samsung,exynosautov920-ufs-phy
> >        - tesla,fsd-ufs-phy
> >
> >    reg:
> > --
> > 2.45.2
> 

Re: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[Krzysztof Kozlowski]

On 18/11/2024 03:10, Sowon Na wrote:
> Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Read carefully guides before posting new versions. You already got one
such reminder, how many are needed?

<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.
</form letter>

Best regards,
Krzysztof

RE: [PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs phy driver

[Alim Akhtar]

Hi Sowon

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Monday, November 18, 2024 7:40 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs phy
> driver
> 
> Add support for ExynosAutov920 ufs phy driver.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

.
.
.
>  drivers/phy/samsung/Makefile                 |   1 +
>  drivers/phy/samsung/phy-exynosautov920-ufs.c | 167
> --
> 2.45.2

RE: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC

[Alim Akhtar]

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Monday, November 18, 2024 7:40 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for
> ExynosAutov920 SoC
> 
> Add UFS Phy for ExynosAutov920
> 
> Like ExynosAutov9, this also uses fixed-rate clock nodes until clock driver has
> been supported. The clock nodes are initialized on bootloader stage thus we
> don't need to control them so far.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

Are you planning to send UFS HCI patches as well?


>  arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index c759134c909e..505ba04722de 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -361,6 +361,17 @@ pinctrl_aud: pinctrl@1a460000 {
>  			compatible = "samsung,exynosautov920-pinctrl";
>  			reg = <0x1a460000 0x10000>;
>  		};
> +
> +		ufs_0_phy: phy@16e04000 {
> +			compatible = "samsung,exynosautov920-ufs-phy";
> +			reg = <0x16e04000 0x4000>;
> +			reg-names = "phy-pma";
> +			clocks = <&xtcxo>;
> +			clock-names = "ref_clk";
> +			samsung,pmu-syscon = <&pmu_system_controller>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
>  	};
> 
>  	timer {
> --
> 2.45.2

RE: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC

[나소원/SOWON NA]

Hi Alim,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Wednesday, November 27, 2024 11:47 AM
> To: 'Sowon Na' <sowon.na@samsung.com>; robh@kernel.org; krzk@kernel.org;
> conor+dt@kernel.org; vkoul@kernel.org; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org
> Subject: RE: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for
> ExynosAutov920 SoC
> 
> 
> 
> > -----Original Message-----
> > From: Sowon Na <sowon.na@samsung.com>
> > Sent: Monday, November 18, 2024 7:40 AM
> > To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> > vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > sowon.na@samsung.com
> > Subject: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for
> > ExynosAutov920 SoC
> >
> > Add UFS Phy for ExynosAutov920
> >
> > Like ExynosAutov9, this also uses fixed-rate clock nodes until clock
> > driver has been supported. The clock nodes are initialized on
> > bootloader stage thus we don't need to control them so far.
> >
> > Signed-off-by: Sowon Na <sowon.na@samsung.com>
> > ---
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> 
> Are you planning to send UFS HCI patches as well?

Yes, I will send UFS HCI patches for ExynosAutov920 after phy patches.
Really thank you for your reviews.

> 
> >  arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index c759134c909e..505ba04722de 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -361,6 +361,17 @@ pinctrl_aud: pinctrl@1a460000 {
> >  			compatible = "samsung,exynosautov920-pinctrl";
> >  			reg = <0x1a460000 0x10000>;
> >  		};
> > +
> > +		ufs_0_phy: phy@16e04000 {
> > +			compatible = "samsung,exynosautov920-ufs-phy";
> > +			reg = <0x16e04000 0x4000>;
> > +			reg-names = "phy-pma";
> > +			clocks = <&xtcxo>;
> > +			clock-names = "ref_clk";
> > +			samsung,pmu-syscon = <&pmu_system_controller>;
> > +			#phy-cells = <0>;
> > +			status = "disabled";
> > +		};
> >  	};
> >
> >  	timer {
> > --
> > 2.45.2
> 

RE: [PATCH v3 0/3] Support ExynosAutov920 ufs phy driver

[나소원/SOWON NA]

Hi Krzysztof, Vinod,


> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Monday, November 18, 2024 11:10 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH v3 0/3] Support ExynosAutov920 ufs phy driver
> 
> This patchset introduces ExynosAuto v920 SoC ufs phy driver as Generic PHY
> driver framework.
> 
> Changes from v2:
> - simplify function name from samsung_exynosautov920_ufs_phy_wait_cdr_lock
>   to exynosautov920_ufs_phy_wait_cdr_lock
> - return immediately after getting the CDR lock
> - add comment for wait CDR lock
> 
> Changes from v1:
> - use exynosautov920 instead of exynosauto to specify
> - remove obvious comment
> - change soc name as ExynosAutov920 to keep consistent
> - use macros instead of magic numbers
> - specify function name
> - add error handling for CDR lock failure
> 
> Sowon Na (3):
>   dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
>   phy: samsung-ufs: support ExynosAutov920 ufs phy driver
>   arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
> 
>  .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi |  11 ++
>  drivers/phy/samsung/Makefile                  |   1 +
>  drivers/phy/samsung/phy-exynosautov920-ufs.c  | 167 ++++++++++++++++++
>  drivers/phy/samsung/phy-samsung-ufs.c         |   9 +-
>  drivers/phy/samsung/phy-samsung-ufs.h         |   4 +
>  6 files changed, 190 insertions(+), 3 deletions(-)  create mode 100644
> drivers/phy/samsung/phy-exynosautov920-ufs.c
> 
> --
> 2.45.2
> 

I can't see these patches in -next, do let me know if anything is missing to be addressed from myside.

Best regards,
Sowon Na.

Re: [PATCH v3 0/3] Support ExynosAutov920 ufs phy driver

[Krzysztof Kozlowski]

On 17/12/2024 02:29, 나소원/SOWON NA wrote:
>>
>> Sowon Na (3):
>>   dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
>>   phy: samsung-ufs: support ExynosAutov920 ufs phy driver
>>   arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
>>
>>  .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
>>  .../arm64/boot/dts/exynos/exynosautov920.dtsi |  11 ++
>>  drivers/phy/samsung/Makefile                  |   1 +
>>  drivers/phy/samsung/phy-exynosautov920-ufs.c  | 167 ++++++++++++++++++
>>  drivers/phy/samsung/phy-samsung-ufs.c         |   9 +-
>>  drivers/phy/samsung/phy-samsung-ufs.h         |   4 +
>>  6 files changed, 190 insertions(+), 3 deletions(-)  create mode 100644
>> drivers/phy/samsung/phy-exynosautov920-ufs.c
>>
>> --
>> 2.45.2
>>
> 
> I can't see these patches in -next, do let me know if anything is missing to be addressed from myside.

I take DTS changes only after bindings got accepted. I think they were
not accepted.

Best regards,
Krzysztof

RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[나소원/SOWON NA]

Hi Krzysztof,

> -----Original Message-----
> From: 나소원/SOWON NA <sowon.na@samsung.com>
> Sent: Tuesday, November 19, 2024 3:36 PM
> To: 'Alim Akhtar' <alim.akhtar@samsung.com>
> Cc: 'robh@kernel.org' <robh@kernel.org>; 'krzk@kernel.org'
> <krzk@kernel.org>; 'conor+dt@kernel.org' <conor+dt@kernel.org>;
> 'vkoul@kernel.org' <vkoul@kernel.org>; 'kishon@kernel.org'
> <kishon@kernel.org>; 'krzk+dt@kernel.org' <krzk+dt@kernel.org>; 'linux-
> kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>;
> 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-samsung-
> soc@vger.kernel.org' <linux-samsung-soc@vger.kernel.org>; 'Krzysztof
> Kozlowski' <krzysztof.kozlowski@linaro.org>
> Subject: RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> bindings
> 
> Hi Alim,
> 
> On 11/19/24 2:21 PM, Alim Akhtar wrote:
> > -----Original Message-----
> > From: Alim Akhtar <alim.akhtar@samsung.com>
> > Sent: Tuesday, November 19, 2024 2:21 PM
> > To: 'Sowon Na' <sowon.na@samsung.com>; robh@kernel.org;
> > krzk@kernel.org;
> > conor+dt@kernel.org; vkoul@kernel.org; kishon@kernel.org
> > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > 'Krzysztof Kozlowski' <krzysztof.kozlowski@linaro.org>
> > Subject: RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS
> > PHY bindings
> >
> >
> >
> > > -----Original Message-----
> > > From: Sowon Na <sowon.na@samsung.com>
> > > Sent: Monday, November 18, 2024 7:40 AM
> > > To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> > > vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> > > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > > sowon.na@samsung.com; Krzysztof Kozlowski
> > > <krzysztof.kozlowski@linaro.org>
> > > Subject: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> > > bindings
> > >
> > > Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.
> > >
> > > Signed-off-by: Sowon Na <sowon.na@samsung.com>
> > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > > ---
> > I am not sure how we can help you, you are keep missing to collect all
> > the tags
> > https://lkml.org/lkml/2024/11/7/617
> >
> Really sorry for missing tags. I append it immediately, and will not miss
> anymore.
> Your review helps me a lot and makes my patch better. I applied all your
> reviews to my patches.
> 
> Thank you a lot once again for your help.
> 

I missed including the "Reviewed-by" tag in the patch set I sent. Could you please let me know if you'd prefer me to send a v4 with the tag included, or if you're able to apply it with the missing tag?

Thank you for your understanding, and I apologize for the oversight.

Best regards,
Sowon.

Re: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[Krzysztof Kozlowski]

On 18/12/2024 02:32, 나소원/SOWON NA wrote:
>>> I am not sure how we can help you, you are keep missing to collect all
>>> the tags
>>> https://lkml.org/lkml/2024/11/7/617
>>>
>> Really sorry for missing tags. I append it immediately, and will not miss
>> anymore.
>> Your review helps me a lot and makes my patch better. I applied all your
>> reviews to my patches.
>>
>> Thank you a lot once again for your help.
>>
> 
> I missed including the "Reviewed-by" tag in the patch set I sent. Could you please let me know if you'd prefer me to send a v4 with the tag included, or if you're able to apply it with the missing tag?
> 
> Thank you for your understanding, and I apologize for the oversight.

Why are you asking me? This is not a patch for me.

Best regards,
Krzysztof

Re: [PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs phy driver

[Vinod Koul]

On 18-11-24, 11:10, Sowon Na wrote:
> Add support for ExynosAutov920 ufs phy driver.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
>  drivers/phy/samsung/Makefile                 |   1 +
>  drivers/phy/samsung/phy-exynosautov920-ufs.c | 167 +++++++++++++++++++
>  drivers/phy/samsung/phy-samsung-ufs.c        |   9 +-
>  drivers/phy/samsung/phy-samsung-ufs.h        |   4 +
>  4 files changed, 178 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/phy/samsung/phy-exynosautov920-ufs.c
> 
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index fea1f96d0e43..342682638a87 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -7,6 +7,7 @@ phy-exynos-ufs-y			+= phy-gs101-ufs.o
>  phy-exynos-ufs-y			+= phy-samsung-ufs.o
>  phy-exynos-ufs-y			+= phy-exynos7-ufs.o
>  phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
> +phy-exynos-ufs-y			+= phy-exynosautov920-ufs.o
>  phy-exynos-ufs-y			+= phy-fsd-ufs.o
>  obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
>  phy-exynos-usb2-y			+= phy-samsung-usb2.o
> diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c b/drivers/phy/samsung/phy-exynosautov920-ufs.c
> new file mode 100644
> index 000000000000..8a7ba159bbfe
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver data for Samsung ExynosAuto v920 SoC
> + *
> + * Copyright (C) 2024 Samsung Electronics Co., Ltd.
> + */
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL			0x708
> +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK		0x1
> +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
> +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
> +
> +#define EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xCE4

Lower case please, here and everywhere else

> +
> +#define PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
> +#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
> +	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
> +
> +/* Calibration for phy initialization */
> +static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
> +	PHY_COMN_REG_CFG(0x29, 0x22, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x04, 0x95, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x06, 0x30, PWR_MODE_ANY),
> +
> +	PHY_TRSV_REG_CFG_AUTOV920(0x200, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x201, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0A, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0C, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2E1, 0xC0, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x22D, 0xF8, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x234, 0x60, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x238, 0x13, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x239, 0x48, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23A, 0x01, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23B, 0x29, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23C, 0x2A, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23D, 0x01, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23E, 0x14, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x23F, 0x13, PWR_MODE_ANY),
> +
> +	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4A, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x25D, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x25E, 0x3F, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x25F, 0xFF, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x26F, 0xF0, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x273, 0x33, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x274, 0x50, PWR_MODE_ANY),
> +
> +	PHY_TRSV_REG_CFG_AUTOV920(0x284, 0x02, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x285, 0x02, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2A2, 0x04, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x27D, 0x01, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2FA, 0x01, PWR_MODE_ANY),
> +
> +	PHY_TRSV_REG_CFG_AUTOV920(0x286, 0x03, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x287, 0x03, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x288, 0x03, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x289, 0x03, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2B3, 0x04, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2B6, 0x0B, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2B7, 0x0B, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2B8, 0x0B, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2B9, 0x0B, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2BA, 0x0B, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2BB, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2BC, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2BD, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x2BE, 0x06, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x34B, 0x01, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x34C, 0x24, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x34D, 0x23, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x34E, 0x45, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x34F, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x350, 0x31, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x351, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x352, 0x02, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x353, 0x00, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x354, 0x01, PWR_MODE_ANY),
> +
> +	PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
> +	PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
> +
> +	END_UFS_PHY_CFG,
> +};
> +
> +/* Calibration for HS mode series A/B */
> +static const struct samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {
> +	PHY_TRSV_REG_CFG_AUTOV920(0x369, 0x11, PWR_MODE_ANY),
> +	PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x03, PWR_MODE_ANY),
> +
> +	END_UFS_PHY_CFG,
> +};
> +
> +static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
> +	END_UFS_PHY_CFG,
> +};
> +
> +#define DELAY_IN_US	40
> +#define RETRY_CNT	100
> +#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8

empty line here please

> +int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
> +{
> +	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> +	u32 reg, i;
> +
> +	struct samsung_ufs_phy_cfg cfg[4] = {
> +		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
> +		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
> +		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
> +		END_UFS_PHY_CFG,
> +	};
> +
> +	for (i = 0; i < RETRY_CNT; i++) {
> +		udelay(DELAY_IN_US);
> +
> +		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
> +			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
> +
> +		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
> +					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
> +			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
> +			return 0;
> +		}
> +
> +		udelay(DELAY_IN_US);
> +
> +		/* Disable and enable CDR */
> +		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
> +		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
> +	}
> +
> +	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
> +	return -ETIMEDOUT;
> +}
> +
> +static const struct samsung_ufs_phy_cfg *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {
> +	[CFG_PRE_INIT]          = exynosautov920_pre_init_cfg,
> +	[CFG_PRE_PWR_HS]        = exynosautov920_pre_pwr_hs_cfg,
> +	[CFG_POST_PWR_HS]       = exynosautov920_post_pwr_hs_cfg,
> +};
> +
> +static const char * const exynosautov920_ufs_phy_clks[] = {
> +	"ref_clk",
> +};
> +
> +const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
> +	.cfgs = exynosautov920_ufs_phy_cfgs,
> +	.isol = {
> +		.offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL,
> +		.mask = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK,
> +		.en = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN,
> +	},
> +	.clk_list = exynosautov920_ufs_phy_clks,
> +	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
> +	.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> +	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
> +};
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> index 6c5d41552649..c13fe149bc75 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -28,9 +28,9 @@
>  
>  #define PHY_DEF_LANE_CNT	1
>  
> -static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> -				   const struct samsung_ufs_phy_cfg *cfg,
> -				   u8 lane)
> +void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> +			    const struct samsung_ufs_phy_cfg *cfg,
> +			    u8 lane)
>  {
>  	enum {LANE_0, LANE_1}; /* lane index */
>  
> @@ -323,6 +323,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
>  	}, {
>  		.compatible = "samsung,exynosautov9-ufs-phy",
>  		.data = &exynosautov9_ufs_phy,
> +	}, {
> +		.compatible = "samsung,exynosautov920-ufs-phy",
> +		.data = &exynosautov920_ufs_phy,
>  	}, {
>  		.compatible = "tesla,fsd-ufs-phy",
>  		.data = &fsd_ufs_phy,
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
> index 9b7deef6e10f..a28f148081d1 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.h
> +++ b/drivers/phy/samsung/phy-samsung-ufs.h
> @@ -143,9 +143,13 @@ static inline void samsung_ufs_phy_ctrl_isol(
>  }
>  
>  int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
> +int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
> +void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> +			    const struct samsung_ufs_phy_cfg *cfg, u8 lane);
>  
>  extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
>  extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
> +extern const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy;
>  extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
>  extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;
>  
> -- 
> 2.45.2

-- 
~Vinod

Re: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings

[Vinod Koul]

On 18-12-24, 10:32, 나소원/SOWON NA wrote:
> Hi Krzysztof,
> 
> > -----Original Message-----
> > From: 나소원/SOWON NA <sowon.na@samsung.com>
> > Sent: Tuesday, November 19, 2024 3:36 PM
> > To: 'Alim Akhtar' <alim.akhtar@samsung.com>
> > Cc: 'robh@kernel.org' <robh@kernel.org>; 'krzk@kernel.org'
> > <krzk@kernel.org>; 'conor+dt@kernel.org' <conor+dt@kernel.org>;
> > 'vkoul@kernel.org' <vkoul@kernel.org>; 'kishon@kernel.org'
> > <kishon@kernel.org>; 'krzk+dt@kernel.org' <krzk+dt@kernel.org>; 'linux-
> > kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>;
> > 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-samsung-
> > soc@vger.kernel.org' <linux-samsung-soc@vger.kernel.org>; 'Krzysztof
> > Kozlowski' <krzysztof.kozlowski@linaro.org>
> > Subject: RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> > bindings
> > 
> > Hi Alim,
> > 
> > On 11/19/24 2:21 PM, Alim Akhtar wrote:
> > > -----Original Message-----
> > > From: Alim Akhtar <alim.akhtar@samsung.com>
> > > Sent: Tuesday, November 19, 2024 2:21 PM
> > > To: 'Sowon Na' <sowon.na@samsung.com>; robh@kernel.org;
> > > krzk@kernel.org;
> > > conor+dt@kernel.org; vkoul@kernel.org; kishon@kernel.org
> > > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > > 'Krzysztof Kozlowski' <krzysztof.kozlowski@linaro.org>
> > > Subject: RE: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS
> > > PHY bindings
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Sowon Na <sowon.na@samsung.com>
> > > > Sent: Monday, November 18, 2024 7:40 AM
> > > > To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> > > > vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> > > > Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> > > > devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> > > > sowon.na@samsung.com; Krzysztof Kozlowski
> > > > <krzysztof.kozlowski@linaro.org>
> > > > Subject: [PATCH v3 1/3] dt-bindings: phy: Add ExynosAutov920 UFS PHY
> > > > bindings
> > > >
> > > > Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.
> > > >
> > > > Signed-off-by: Sowon Na <sowon.na@samsung.com>
> > > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > > > ---
> > > I am not sure how we can help you, you are keep missing to collect all
> > > the tags
> > > https://lkml.org/lkml/2024/11/7/617
> > >
> > Really sorry for missing tags. I append it immediately, and will not miss
> > anymore.
> > Your review helps me a lot and makes my patch better. I applied all your
> > reviews to my patches.
> > 
> > Thank you a lot once again for your help.
> > 
> 
> I missed including the "Reviewed-by" tag in the patch set I sent.
> Could you please let me know if you'd prefer me to send a v4 with the
> tag included, or if you're able to apply it with the missing tag?

Please wrap your replies in 80chars

Yes pls add and post v4

> 
> Thank you for your understanding, and I apologize for the oversight.
> 
> Best regards,
> Sowon.
> 
> 

-- 
~Vinod

RE: [PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs phy driver

[나소원/SOWON NA]

Hi Vinod,

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Tuesday, December 24, 2024 11:59 PM
> To: Sowon Na <sowon.na@samsung.com>
> Cc: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> alim.akhtar@samsung.com; kishon@kernel.org; krzk+dt@kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-samsung-
> soc@vger.kernel.org
> Subject: Re: [PATCH v3 2/3] phy: samsung-ufs: support ExynosAutov920 ufs
> phy driver
> 
> On 18-11-24, 11:10, Sowon Na wrote:
> > Add support for ExynosAutov920 ufs phy driver.
> >
> > Signed-off-by: Sowon Na <sowon.na@samsung.com>
> > ---
> >  drivers/phy/samsung/Makefile                 |   1 +
> >  drivers/phy/samsung/phy-exynosautov920-ufs.c | 167 +++++++++++++++++++
> >  drivers/phy/samsung/phy-samsung-ufs.c        |   9 +-
> >  drivers/phy/samsung/phy-samsung-ufs.h        |   4 +
> >  4 files changed, 178 insertions(+), 3 deletions(-)  create mode
> > 100644 drivers/phy/samsung/phy-exynosautov920-ufs.c
> >
> > diff --git a/drivers/phy/samsung/Makefile
> > b/drivers/phy/samsung/Makefile index fea1f96d0e43..342682638a87 100644
> > --- a/drivers/phy/samsung/Makefile
> > +++ b/drivers/phy/samsung/Makefile
> > @@ -7,6 +7,7 @@ phy-exynos-ufs-y			+= phy-gs101-ufs.o
> >  phy-exynos-ufs-y			+= phy-samsung-ufs.o
> >  phy-exynos-ufs-y			+= phy-exynos7-ufs.o
> >  phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
> > +phy-exynos-ufs-y			+= phy-exynosautov920-ufs.o
> >  phy-exynos-ufs-y			+= phy-fsd-ufs.o
> >  obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
> >  phy-exynos-usb2-y			+= phy-samsung-usb2.o
> > diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c
> > b/drivers/phy/samsung/phy-exynosautov920-ufs.c
> > new file mode 100644
> > index 000000000000..8a7ba159bbfe
> > --- /dev/null
> > +++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c
> > @@ -0,0 +1,167 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * UFS PHY driver data for Samsung ExynosAuto v920 SoC
> > + *
> > + * Copyright (C) 2024 Samsung Electronics Co., Ltd.
> > + */
> > +
> > +#include "phy-samsung-ufs.h"
> > +
> > +#define
EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL			0x708
> > +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK		0x1
> > +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
> > +#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
> > +
> > +#define
EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xCE4
> 
> Lower case please, here and everywhere else

Okay, I will fix.

> > +
> > +#define
PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
> > +#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
> > +	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
> > +
> > +/* Calibration for phy initialization */ static const struct
> > +samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
> > +	PHY_COMN_REG_CFG(0x29, 0x22, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x04, 0x95, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x06, 0x30, PWR_MODE_ANY),
> > +
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x200, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x201, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0A, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0C, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2E1, 0xC0, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x22D, 0xF8, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x234, 0x60, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x238, 0x13, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x239, 0x48, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23A, 0x01, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23B, 0x29, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23C, 0x2A, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23D, 0x01, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23E, 0x14, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x23F, 0x13, PWR_MODE_ANY),
> > +
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4A, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x25D, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x25E, 0x3F, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x25F, 0xFF, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x26F, 0xF0, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x273, 0x33, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x274, 0x50, PWR_MODE_ANY),
> > +
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x284, 0x02, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x285, 0x02, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2A2, 0x04, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x27D, 0x01, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2FA, 0x01, PWR_MODE_ANY),
> > +
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x286, 0x03, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x287, 0x03, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x288, 0x03, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x289, 0x03, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2B3, 0x04, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2B6, 0x0B, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2B7, 0x0B, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2B8, 0x0B, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2B9, 0x0B, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2BA, 0x0B, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2BB, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2BC, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2BD, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x2BE, 0x06, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x34B, 0x01, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x34C, 0x24, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x34D, 0x23, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x34E, 0x45, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x34F, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x350, 0x31, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x351, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x352, 0x02, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x353, 0x00, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x354, 0x01, PWR_MODE_ANY),
> > +
> > +	PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
> > +	PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
> > +
> > +	END_UFS_PHY_CFG,
> > +};
> > +
> > +/* Calibration for HS mode series A/B */ static const struct
> > +samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x369, 0x11, PWR_MODE_ANY),
> > +	PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x03, PWR_MODE_ANY),
> > +
> > +	END_UFS_PHY_CFG,
> > +};
> > +
> > +static const struct samsung_ufs_phy_cfg
exynosautov920_post_pwr_hs_cfg[]
> = {
> > +	END_UFS_PHY_CFG,
> > +};
> > +
> > +#define DELAY_IN_US	40
> > +#define RETRY_CNT	100
> > +#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8
> 
> empty line here please

I will post v4 with modifications.
Thank you.

> > +int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane) {
> > +	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > +	u32 reg, i;
> > +
> > +	struct samsung_ufs_phy_cfg cfg[4] = {
> > +		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
> > +		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
> > +		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
> > +		END_UFS_PHY_CFG,
> > +	};
> > +
> > +	for (i = 0; i < RETRY_CNT; i++) {
> > +		udelay(DELAY_IN_US);
> > +
> > +		reg = readl(ufs_phy->reg_pma +
> EXYNOSAUTOV920_CDR_LOCK_OFFSET +
> > +			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) *
lane));
> > +
> > +		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
> > +					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
> > +			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
> > +			return 0;
> > +		}
> > +
> > +		udelay(DELAY_IN_US);
> > +
> > +		/* Disable and enable CDR */
> > +		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
> > +		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
> > +	}
> > +
> > +	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
> > +	return -ETIMEDOUT;
> > +}
> > +
> > +static const struct samsung_ufs_phy_cfg
> *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {
> > +	[CFG_PRE_INIT]          = exynosautov920_pre_init_cfg,
> > +	[CFG_PRE_PWR_HS]        = exynosautov920_pre_pwr_hs_cfg,
> > +	[CFG_POST_PWR_HS]       = exynosautov920_post_pwr_hs_cfg,
> > +};
> > +
> > +static const char * const exynosautov920_ufs_phy_clks[] = {
> > +	"ref_clk",
> > +};
> > +
> > +const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
> > +	.cfgs = exynosautov920_ufs_phy_cfgs,
> > +	.isol = {
> > +		.offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL,
> > +		.mask = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK,
> > +		.en = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN,
> > +	},
> > +	.clk_list = exynosautov920_ufs_phy_clks,
> > +	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
> > +	.cdr_lock_status_offset =
> EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> > +	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
> > +};
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> > b/drivers/phy/samsung/phy-samsung-ufs.c
> > index 6c5d41552649..c13fe149bc75 100644
> > --- a/drivers/phy/samsung/phy-samsung-ufs.c
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> > @@ -28,9 +28,9 @@
> >
> >  #define PHY_DEF_LANE_CNT	1
> >
> > -static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> > -				   const struct samsung_ufs_phy_cfg *cfg,
> > -				   u8 lane)
> > +void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> > +			    const struct samsung_ufs_phy_cfg *cfg,
> > +			    u8 lane)
> >  {
> >  	enum {LANE_0, LANE_1}; /* lane index */
> >
> > @@ -323,6 +323,9 @@ static const struct of_device_id
> samsung_ufs_phy_match[] = {
> >  	}, {
> >  		.compatible = "samsung,exynosautov9-ufs-phy",
> >  		.data = &exynosautov9_ufs_phy,
> > +	}, {
> > +		.compatible = "samsung,exynosautov920-ufs-phy",
> > +		.data = &exynosautov920_ufs_phy,
> >  	}, {
> >  		.compatible = "tesla,fsd-ufs-phy",
> >  		.data = &fsd_ufs_phy,
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.h
> > b/drivers/phy/samsung/phy-samsung-ufs.h
> > index 9b7deef6e10f..a28f148081d1 100644
> > --- a/drivers/phy/samsung/phy-samsung-ufs.h
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.h
> > @@ -143,9 +143,13 @@ static inline void samsung_ufs_phy_ctrl_isol(  }
> >
> >  int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
> > +int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
> > +void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> > +			    const struct samsung_ufs_phy_cfg *cfg, u8 lane);
> >
> >  extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;  extern
> > const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
> > +extern const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy;
> >  extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;  extern
> > const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;
> >
> > --
> > 2.45.2
> 
> --
> ~Vinod

Best regards,
Sowon