From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29278C433EF for ; Mon, 11 Apr 2022 12:20:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230290AbiDKMXF (ORCPT ); Mon, 11 Apr 2022 08:23:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346104AbiDKMWy (ORCPT ); Mon, 11 Apr 2022 08:22:54 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0686542A0D for ; Mon, 11 Apr 2022 05:20:38 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ndt1s-0004DP-Bg; Mon, 11 Apr 2022 14:20:24 +0200 Message-ID: Subject: Re: [PATCH v0 07/10] phy: freescale: add Samsung HDMI PHY From: Lucas Stach To: Maxime Ripard Cc: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Shawn Guo , NXP Linux Team , Fabio Estevam , Pengutronix Kernel Team , Robert Foss , Neil Armstrong , Andrzej Hajda , Vinod Koul , Kishon Vijay Abraham I , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, patchwork-lst@pengutronix.de Date: Mon, 11 Apr 2022 14:20:22 +0200 In-Reply-To: <20220411115922.luv2gyutdecvsxa3@houat> References: <20220406160123.1272911-1-l.stach@pengutronix.de> <20220406160123.1272911-8-l.stach@pengutronix.de> <20220411115922.luv2gyutdecvsxa3@houat> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Maxime, Am Montag, dem 11.04.2022 um 13:59 +0200 schrieb Maxime Ripard: > Hi Lucas, > > On Wed, Apr 06, 2022 at 06:01:20PM +0200, Lucas Stach wrote: > > +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, > > + unsigned long parent_rate) > > +{ > > + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); > > + > > + if (!phy->cur_cfg) > > + return 0; > > + > > + return phy->cur_cfg->clk_rate; > > +} > > This means that the clock will return 0 at initialization, which will > throw the rate accounting in the CCF off. > > Returning 0 here isn't valid. Surely that phy has a default > configuration at boot that you could use to initialize a rate? > > See https://lore.kernel.org/linux-clk/20220408091037.2041955-1-maxime@cerno.tech/ Thanks for the hint. I don't know the full history of this and surely I can use the register reset defaults to initialize the clock rate, but it still seems odd. A powered down clock generator, like the PLL in this PHY, is not actually putting out a clock at any rate, so 0 for the rate seems natural, so it's kind of a bad pitfall if the CCF can't deal with that. Regards, Lucas