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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDExNyBTYWx0ZWRfX49/+3s/iJceN mWZYN/UJvwq2amy0nzK/Xlmr3aAuNUEnrsTlFpoL6UKjJI3zt0k69m6yHxaoYbjBrlbCNEXKxsH 2OG/WV6Ebbt77q0UzbmDKZ0yZlu8zF+4GDJu65Ntxsj0J87eqweyZNuO7D2YyeucdzaVRWuXWAi 0w2wUNM/MuDgsvBxuO9PKgw8BTY6qZrPvSQD/wlUye2V3MUM4S1578yM0opyVBCRQwkqopsDmro dg8vTZiwNhU3EZDPctwuQ8PUTpJtegb0DkMtLOvNzMB6YV8raph2hQZ4+SMtozLSjmRpT5pRGWs EOpJDI//ITDjyoFe3EuUj5EXLuhuWRNDLe/BGksBjBK1DjAyt+Uvx7VCRsQK13eEy9He7Hj+5rd W/DdmeSIRjleRgAo4paVVYeOcpcq8bp6HqmjYgnLAC7v9lnZYrZx28682gr+aDDej0a1KUYjA29 c77zK4GRS+F+gzOj3sQ== X-Authority-Analysis: v=2.4 cv=L6ItheT8 c=1 sm=1 tr=0 ts=6a96d1c7 cx=c_pps a=+D9SDfe9YZWTjADjLiQY5g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=UqCG9HQmAAAA:8 a=B9jzo3DVsI2-tMNqGVoA:9 a=QEXdDO2ut3YA:10 a=vmgOmaN-Xu0dpDh8OwbV:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDExNyBTYWx0ZWRfX+uWR82lzshzB d+uKo/65reDvPsuLCaYlLlq/CE6S2vTzH1Q9JQBsFlNoj9osPTJt5rGMwcUgblISgLlQYcOrPkR dxWo1+CwQOK5Ehks8cjzq0Lm5Pk4khM= X-Proofpoint-ORIG-GUID: dZzv5gQGCeN0Wd5uiyYvA9u77iH2a6VN X-Proofpoint-GUID: dZzv5gQGCeN0Wd5uiyYvA9u77iH2a6VN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_03,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010117 On 8/25/26 2:37 PM, George Moussalem via B4 Relay wrote: > From: George Moussalem > > Add support for the USB3 PHY on IPQ5018 chipsets. > > The PHY outputs a 250MHz PIPE clock routed to and gated by the GCC, so > register a fixed rate clock. In addition, add the register/value pairs > for the PHY initialization sequence. > > The PHY requires a 5V supply, so acquire the regulator from the > devicetree and enable it on power on and disable it on power off. > > The code to acquire clocks and resets is the same as for PCIe so no > changes are needed. > > Power on/off sequences for PCIE and USB3 are similar except for the > delay timings and USB3 requirement for the PHY supply. > > Lastly, the PCIe and USB3 pads are muxed so select USB3 mode in TCSR > which needs to occur before the DWC3 USB3 controller resets. > Otherwise, the SS link doesn't train and remains stuck in RX.Detect. > > Signed-off-by: George Moussalem > --- Let's register both PHYs (#phy-cells = <1>), but only make one accessible. Otherwise, we'd need to alter the compatible to access the PCIe part. Konrad