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[109.252.138.126]) by smtp.googlemail.com with ESMTPSA id bu32sm3224069lfb.287.2022.01.30.02.33.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Jan 2022 02:33:52 -0800 (PST) Message-ID: Date: Sun, 30 Jan 2022 13:33:51 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v17 2/4] dmaengine: tegra: Add tegra gpcdma driver Content-Language: en-US From: Dmitry Osipenko To: Akhil R , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, jonathanh@nvidia.com, kyarlagadda@nvidia.com, ldewangan@nvidia.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, p.zabel@pengutronix.de, rgumasta@nvidia.com, robh+dt@kernel.org, thierry.reding@gmail.com, vkoul@kernel.org Cc: Pavan Kunapuli References: <1643474453-32619-1-git-send-email-akhilrajeev@nvidia.com> <1643474453-32619-3-git-send-email-akhilrajeev@nvidia.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 30.01.2022 13:26, Dmitry Osipenko пишет: > 30.01.2022 13:05, Dmitry Osipenko пишет: >> Still nothing prevents interrupt handler to fire during the pause. >> >> What you actually need to do is to disable/enable interrupt. This will >> prevent the interrupt racing and then pause/resume may look like this: > > Although, seems this won't work, unfortunately. I see now that > device_pause() doesn't have might_sleep(). > Ah, I see now that the pause/unpause is actually a separate control and doesn't conflict with "start next transfer". So you just need to set/unset the pause under lock. And don't touch tdc->dma_desc. That's it. static int tegra_dma_device_pause(struct dma_chan *dc) { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); unsigned long flags; u32 val; if (!tdc->tdma->chip_data->hw_support_pause) return -ENOSYS; spin_lock_irqsave(&tdc->vc.lock, flags); val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE; tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); spin_unlock_irqrestore(&tdc->vc.lock, flags); return 0; } static int tegra_dma_device_resume(struct dma_chan *dc) { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); unsigned long flags; u32 val; if (!tdc->tdma->chip_data->hw_support_pause) return -ENOSYS; spin_lock_irqsave(&tdc->vc.lock, flags); val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); spin_unlock_irqrestore(&tdc->vc.lock, flags); return 0; }