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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: lMZoFHAhpSOpLehFfSMVtjshQP1_G3Fh X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDExMCBTYWx0ZWRfX3h0UgKAFTwxh q8qUXNaLYX/AyDJ4yNKaiKnYiWjokhSz/mERIl3Wu1hkUJGx08ytJX5RwofaU02sAkB8YzUJgQe E5hMY5Uk8/3/Tb7NMLg/42M2FCnucGE= X-Proofpoint-GUID: lMZoFHAhpSOpLehFfSMVtjshQP1_G3Fh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDExMCBTYWx0ZWRfX2RP7UkJV+HRY dtj1gsyjdwt8N3mBJqUhoiHHNdKapLZuusuNlGiYlTGcQV6miVw65uxuG5+e8vlombIGV/vT86o XboAgT6FZEtBV9PfGYwjrbZhQTaq5BZE0mHekHc/kiPa4S+ByrwNQ+0zK4Lic/vASSNh7Kqx30u XrPUh7/4IR0uifWkhwnBdpsLrGL7YNP2anaxASR0DSGbEAAow59hjvTBpNkDIOmlgvbcpxROnhg cnL3A0rs5vCD6HFKVJbro37fD+TKX+wISb7kbWIB/P/iZq33cNXfmkmjWNl3Q/YLZPpyJWJSK3Y Si3vPBe6TOCnoDiIw5moe1f40PsFzTQK0hBVpgSwPCGqa+1peYWKEzf5/dcZHu13Jm/bP+KaBtW OmStW2VcPs0sCTZzUjgBXFEqH5hM6h6rm0ZbqYQK6K3PVL/B5M1d6O8AAuWR+C0Z5hMbOGdSYIv jvAH0PXx7MPstZX1Y5g== X-Authority-Analysis: v=2.4 cv=PPQ/P/qC c=1 sm=1 tr=0 ts=6a8ee806 cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=TDtJeqXoE0GuUOfqXLQA:9 a=QEXdDO2ut3YA:10 a=XD7yVLdPMpWraOa8Un9W:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_03,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260110 On 8/26/26 4:53 AM, Yongxing Mou wrote: > > > On 8/25/2026 4:30 PM, Konrad Dybcio wrote: >> On 8/25/26 8:28 AM, Yongxing Mou wrote: >>> >>> >>> On 8/17/2026 10:14 PM, Konrad Dybcio wrote: >>>> On 8/17/26 4:13 PM, Konrad Dybcio wrote: >>>>> On 8/13/26 9:44 AM, Yongxing Mou wrote: >>>>>> >>>>>> >>>>>> On 7/20/2026 4:49 PM, Konrad Dybcio wrote: >>>>>>> On 7/20/26 10:43 AM, Yongxing Mou wrote: >>>>>>>> Kaanapali (SM8750) and Glymur use two display power domains. >>>>>>>> CORE_GDSC powers the main display hardware while INT2_GDSC >>>>>>>> powers a subset of SSPP blocks. >>>>>>> >>>>>>> Can they operate independently? Does INT2_GDSC need to be >>>>>>> powered on after CORE_GDSC? >>>>>>> >>>>>> On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused. >>>>> >>>>> Is the MDSS any useful if *only* INT2_GDSC is enabled? Can the INT2_GDSC >>>>> be enabled itself if CORE_GDSC is off? >>>> >>>> (I didn't quite know how to parse the list of states you provided in your >>>> reply so I asked again) >>>> >>>> Konrad >>> Hi, Konard. Would you recommend adding the parent clock in the clock driver, or handling 2 GDSC in the display driver? I'm preparing the next revision and would appreciate your feedback. >> >> Does disabling INT2 provide us with any power benefits and will the > So far, I haven't found any documentation that explicitly describes a power-saving use case achieved by disabling the INT2 GDSC. The material I found instead describes it in the context of display tiering: > "Goal for partial display is to tier down from premium tier to match low tier pipe configurations." >> display driver do the accounting for what resources need the INT2 >> GDSC specifically? > Not at the moment. Our current requirement is simply to enable and disable it together with the core GDSC. So WDYT Dmitry, should we just wire it up as a child of the core gdsc on the clk side and pass just one gdsc to mdss? Konrad