From: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
To: Vincent Guittot <vincent.guittot@linaro.org>,
chester62515@gmail.com, mbrugger@suse.com, s32@nxp.com,
bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
ciprianmarian.costea@oss.nxp.com
Cc: cassel@kernel.org
Subject: Re: [PATCH 4/4 v5] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
Date: Wed, 26 Nov 2025 13:42:57 -0600 [thread overview]
Message-ID: <f38396c7-0605-4876-9ea6-0a179d6577c7@oss.nxp.com> (raw)
In-Reply-To: <20251118160238.26265-5-vincent.guittot@linaro.org>
On 11/18/2025 10:02 AM, Vincent Guittot wrote:
> Add a new entry for S32G PCIe driver.
>
> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e64b94e6b5a9..bec5d5792a5f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3137,6 +3137,15 @@ F: arch/arm64/boot/dts/freescale/s32g*.dts*
> F: drivers/pinctrl/nxp/
> F: drivers/rtc/rtc-s32g.c
>
> +ARM/NXP S32G PCIE CONTROLLER DRIVER
> +M: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> +R: NXP S32 Linux Team <s32@nxp.com>
> +L: imx@lists.linux.dev
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
> +F: Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> +F: drivers/pci/controller/dwc/pcie-nxp-s32g*
Hi Vincent,
Thank you for proposing me as the maintainer for PCIe on S32G.
While I consider myself reasonably experienced with the S32G platform, I
am definitely not a PCIe expert. Therefore, I would prefer Ciprian
Marian Costea (<ciprianmarian.costea@oss.nxp.com>) to maintain this
component, given his expertise in PCIe on S32G.
> +
> ARM/NXP S32G/S32R DWMAC ETHERNET DRIVER
> M: Jan Petrous <jan.petrous@oss.nxp.com>
> R: s32@nxp.com
--
Regards,
Ghennadi
next prev parent reply other threads:[~2025-11-26 19:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 16:02 [PATCH 0/4 v5] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-11-18 16:02 ` [PATCH 1/4 v5] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-11-18 16:52 ` Frank Li
2025-11-20 11:27 ` Manivannan Sadhasivam
2025-11-20 15:23 ` Rob Herring (Arm)
2025-11-18 16:02 ` [PATCH 2/4 v5] PCI: dw: Add more registers and bitfield definition Vincent Guittot
2025-11-18 16:54 ` Frank Li
2025-11-18 16:02 ` [PATCH 3/4 v5] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-11-18 17:01 ` Frank Li
2025-11-20 7:25 ` Vincent Guittot
2025-11-20 8:22 ` Manivannan Sadhasivam
2025-11-20 9:06 ` Vincent Guittot
2025-11-20 10:25 ` Manivannan Sadhasivam
2025-11-20 17:57 ` Vincent Guittot
2025-11-18 16:02 ` [PATCH 4/4 v5] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-11-26 19:42 ` Ghennadi Procopciuc [this message]
2025-11-26 20:17 ` Ciprian Marian Costea
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