From: Krzysztof Kozlowski <krzk@kernel.org>
To: Manikandan Karunakaran Pillai <mpillai@cadence.com>,
Hans Zhang <hans.zhang@cixtech.com>,
Conor Dooley <conor@kernel.org>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kw@linux.com" <kw@linux.com>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"peter.chen@cixtech.com" <peter.chen@cixtech.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations
Date: Sun, 27 Apr 2025 21:08:45 +0200 [thread overview]
Message-ID: <f39ae724-8f5b-4738-9308-995e68adfcf1@kernel.org> (raw)
In-Reply-To: <DS0PR07MB10492178596F396BC1A52BE2FA2862@DS0PR07MB10492.namprd07.prod.outlook.com>
On 27/04/2025 05:55, Manikandan Karunakaran Pillai wrote:
> work.
>>>>>>>
>>>>>>> Same applies to the other binding patch.
>>>>>> Additionally, since this IP is likely in use on your sky1 SoC, why is a
>>>>>> soc-specific compatible for your integration not needed?
>>>>>>
>>>>> The sky1 SoC support patches will be developed and submitted by the
>> Sky1
>>>>> team separately.
>>>> Why? Cixtech sent this patchset, they should send it with their user.
>>>
>>> Hi Conor,
>>>
>>> Please look at the communication history of this website.
>>>
>>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-
>> pci/patch/CH2PPF4D26F8E1C1CBD2A866C59AA55CD7AA2A12@CH2PPF4D26F
>> 8E1C.namprd07.prod.outlook.com/__;!!EHscmS1ygiU1lA!Gh-
>> UeyTbbr2R3ocWWa4QZHM_GYBRXws7a5zc3lZvSy_XYVCkcg8mmeEaAWS4wEvI
>> SMV2tGCEylE$
>>
>> And in that thread I asked for Soc specific compatible. More than once.
>> Conor asks again.
>>
>> I don't understand your answers at all.
>
> The current support is for the IP from Cadence. There can be multiple SoC developed based on this IP and it is for
> the SoC companies to build in support as and when the SoC support needs to be available.
>
> Since the CIX SoC is available, it can be send together with this patch.
> However, I do not understand the need for clubbing these in a single patch.
No one asks for this. The point is such IP blocks are usually customized
per SoC this generic compatibles are not enough. That's the argument
here, not whether you can have multiple vendors (we all know this,
imagine we know Cadence, Synopsys etc) or whether you want to combine
here Cix or not. Answer rather how much software interface is compatible
or common between different implementations.
... AND even then you always need soc specific compatible. See writing
bindings for the reason (or any other tutorial/guide/speech about
writing bindings).
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-04-27 19:08 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-24 1:04 [PATCH v4 0/5] Enhance the PCIe controller driver hans.zhang
2025-04-24 1:04 ` [PATCH v4 1/5] dt-bindings: pci: cadence: Extend compatible for new RP configuration hans.zhang
2025-04-24 1:04 ` [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations hans.zhang
2025-04-24 15:29 ` Conor Dooley
2025-04-24 15:30 ` Conor Dooley
2025-04-25 2:19 ` Manikandan Karunakaran Pillai
2025-04-25 14:48 ` Conor Dooley
2025-04-25 15:33 ` Hans Zhang
2025-04-25 16:21 ` Krzysztof Kozlowski
2025-04-25 16:47 ` Hans Zhang
2025-04-27 3:55 ` Manikandan Karunakaran Pillai
2025-04-27 19:08 ` Krzysztof Kozlowski [this message]
2025-04-25 2:17 ` Manikandan Karunakaran Pillai
2025-04-24 1:04 ` [PATCH v4 3/5] PCI: cadence: Add header support for PCIe HPA controller hans.zhang
2025-04-24 3:36 ` Peter Chen (CIX)
2025-04-25 4:18 ` kernel test robot
2025-04-24 1:04 ` [PATCH v4 4/5] PCI: cadence: Add support for PCIe Endpoint " hans.zhang
2025-04-24 1:04 ` [PATCH v4 5/5] PCI: cadence: Add callback functions for RP and EP controller hans.zhang
2025-04-25 6:01 ` kernel test robot
2025-04-25 16:27 ` Krzysztof Kozlowski
2025-04-25 16:51 ` Hans Zhang
2025-04-27 3:52 ` Manikandan Karunakaran Pillai
2025-06-01 14:40 ` manivannan.sadhasivam
2025-06-02 1:24 ` Manikandan Karunakaran Pillai
2025-04-25 16:24 ` [PATCH v4 0/5] Enhance the PCIe controller driver Krzysztof Kozlowski
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