[PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[Bhavya Kapoor]

This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
J7200 and for DDR50 speed mode for MMCSD in J721s2 and J784s4 SoC.

Rebased to next-20231201

Bhavya Kapoor (3):
  arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed
    mode
  arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed
    mode
  arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed
    mode

 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi  | 1 +
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
 3 files changed, 3 insertions(+)

-- 
2.34.1

[PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode

[Bhavya Kapoor]

DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
is not present in the device tree. Thus, add Itap Delay Value for eMMC
High Speed DDR which is DDR52 speed mode for J7200 SoC according to
datasheet for J7200.

[+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface,  in
	J7200 datasheet
- https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 264913f83287..39ce465c8e00 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -647,6 +647,7 @@ main_sdhci0: mmc@4f80000 {
 		ti,otap-del-sel-hs400 = <0x5>;
 		ti,itap-del-sel-legacy = <0x10>;
 		ti,itap-del-sel-mmc-hs = <0xa>;
+		ti,itap-del-sel-ddr52 = <0x3>;
 		ti,strobe-sel = <0x77>;
 		ti,clkbuf-sel = <0x7>;
 		ti,trm-icp = <0x8>;
-- 
2.34.1

[PATCH 2/3] arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode

[Bhavya Kapoor]

DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC
according to datasheet for J721s2.

[+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface,  in
	J721s2 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b03731b53a26..e1255956288b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -766,6 +766,7 @@ main_sdhci1: mmc@4fb0000 {
 		ti,itap-del-sel-sd-hs = <0x0>;
 		ti,itap-del-sel-sdr12 = <0x0>;
 		ti,itap-del-sel-sdr25 = <0x0>;
+		ti,itap-del-sel-ddr50 = <0x2>;
 		ti,clkbuf-sel = <0x7>;
 		ti,trm-icp = <0x8>;
 		dma-coherent;
-- 
2.34.1

[PATCH 3/3] arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode

[Bhavya Kapoor]

DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4.

[+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
	J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index d89bcddcfe3d..b9a2358b1459 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -712,6 +712,7 @@ main_sdhci1: mmc@4fb0000 {
 		ti,itap-del-sel-sd-hs = <0x0>;
 		ti,itap-del-sel-sdr12 = <0x0>;
 		ti,itap-del-sel-sdr25 = <0x0>;
+		ti,itap-del-sel-ddr50 = <0x2>;
 		ti,clkbuf-sel = <0x7>;
 		ti,trm-icp = <0x8>;
 		dma-coherent;
-- 
2.34.1

Re: [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[Kumar, Udit]

Hi Bhavya

On 12/1/2023 1:50 PM, Bhavya Kapoor wrote:
> This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
> J7200 and for DDR50 speed mode for MMCSD in J721s2 and J784s4 SoC.
>
> Rebased to next-20231201
>
> Bhavya Kapoor (3):
>    arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed
>      mode
>    arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed
>      mode
>    arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed
>      mode

Could you confirm, after adding itap values, above modes are working 
fine apart from

mode detection.

Thanks

Udit


>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi  | 1 +
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
>   3 files changed, 3 insertions(+)
>

Re: [PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode

[Judith Mendez]

Hi Bhavya,

On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
> DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
> is not present in the device tree. Thus, add Itap Delay Value for eMMC
> High Speed DDR which is DDR52 speed mode for J7200 SoC according to
> datasheet for J7200.
> 
> [+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface,  in
> 	J7200 datasheet
> - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
> 

LGTM

Reviewed-by: Judith Mendez <jm@ti.com>

> Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 264913f83287..39ce465c8e00 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -647,6 +647,7 @@ main_sdhci0: mmc@4f80000 {
>   		ti,otap-del-sel-hs400 = <0x5>;
>   		ti,itap-del-sel-legacy = <0x10>;
>   		ti,itap-del-sel-mmc-hs = <0xa>;
> +		ti,itap-del-sel-ddr52 = <0x3>;
>   		ti,strobe-sel = <0x77>;
>   		ti,clkbuf-sel = <0x7>;
>   		ti,trm-icp = <0x8>;

~ Judith

Re: [PATCH 2/3] arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode

[Judith Mendez]

Hi Bhavya,

On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
> DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
> Value is not present in the device tree. Thus, add Itap Delay Value
> for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC
> according to datasheet for J721s2.
> 
> [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface,  in
> 	J721s2 datasheet
> - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
> 

LGTM

Reviewed-by: Judith Mendez <jm@ti.com>

> Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index b03731b53a26..e1255956288b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -766,6 +766,7 @@ main_sdhci1: mmc@4fb0000 {
>   		ti,itap-del-sel-sd-hs = <0x0>;
>   		ti,itap-del-sel-sdr12 = <0x0>;
>   		ti,itap-del-sel-sdr25 = <0x0>;
> +		ti,itap-del-sel-ddr50 = <0x2>;
>   		ti,clkbuf-sel = <0x7>;
>   		ti,trm-icp = <0x8>;
>   		dma-coherent;

~ Judith

Re: [PATCH 3/3] arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode

[Judith Mendez]

Hi Bhavya,

On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
> DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
> Value is not present in the device tree. Thus, add Itap Delay Value
> for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC
> according to datasheet for J784s4.
> 
> [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
> 	J784s4 datasheet
> - https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf
> 

Also looks good. (:

Reviewed-by: Judith Mendez <jm@ti.com>

> Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index d89bcddcfe3d..b9a2358b1459 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -712,6 +712,7 @@ main_sdhci1: mmc@4fb0000 {
>   		ti,itap-del-sel-sd-hs = <0x0>;
>   		ti,itap-del-sel-sdr12 = <0x0>;
>   		ti,itap-del-sel-sdr25 = <0x0>;
> +		ti,itap-del-sel-ddr50 = <0x2>;
>   		ti,clkbuf-sel = <0x7>;
>   		ti,trm-icp = <0x8>;
>   		dma-coherent;

~ Judith

Re: [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[Bhavya Kapoor]

On 06/12/23 12:01 am, Kumar, Udit wrote:
> Hi Bhavya
>
> On 12/1/2023 1:50 PM, Bhavya Kapoor wrote:
>> This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
>> J7200 and for DDR50 speed mode for MMCSD in J721s2 and J784s4 SoC.
>>
>> Rebased to next-20231201
>>
>> Bhavya Kapoor (3):
>>    arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed
>>      mode
>>    arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed
>>      mode
>>    arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed
>>      mode
>
> Could you confirm, after adding itap values, above modes are working 
> fine apart from
>
> mode detection.
>
> Thanks
>
> Udit

Hi Udit, Below are the links to the test logs

j7200 ddr52 - 
https://gist.github.com/a0498981/f9b7b7d3592eaca591dec3e72de45585

j721s2 ddr50 - 
https://gist.github.com/a0498981/9861e1df3fe0fc7c050db4f7a8cc34b8

j784s4 ddr50 - 
https://gist.github.com/a0498981/7c598dd708424252e2629fe0c7458a6d

Thanks

~B-Kapoor

>
>
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi  | 1 +
>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
>>   3 files changed, 3 insertions(+)
>>

Re: [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[Kumar, Udit]

On 12/14/2023 4:37 PM, Bhavya Kapoor wrote:
>
> On 06/12/23 12:01 am, Kumar, Udit wrote:
>> Hi Bhavya
>>
>> On 12/1/2023 1:50 PM, Bhavya Kapoor wrote:
>>> This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
>>> J7200 and for DDR50 speed mode for MMCSD in J721s2 and J784s4 SoC.
>>>
>>> Rebased to next-20231201
>>>
>>> Bhavya Kapoor (3):
>>>    arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed
>>>      mode
>>>    arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed
>>>      mode
>>>    arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed
>>>      mode
>>
>> Could you confirm, after adding itap values, above modes are working 
>> fine apart from
>>
>> mode detection.
>>
>> Thanks
>>
>> Udit
>
> Hi Udit, Below are the links to the test logs
>
> j7200 ddr52 - 
> https://gist.github.com/a0498981/f9b7b7d3592eaca591dec3e72de45585
>
> j721s2 ddr50 - 
> https://gist.github.com/a0498981/9861e1df3fe0fc7c050db4f7a8cc34b8
>
> j784s4 ddr50 - 
> https://gist.github.com/a0498981/7c598dd708424252e2629fe0c7458a6d
>
> Thanks
>
> ~B-Kapoor
>

Thanks for logs Bhavya,

With that for series

Reviewed-by: Udit Kumar <u-kumar1@ti.com>



>>
>>
>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
>>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
>>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
>>>   3 files changed, 3 insertions(+)
>>>

Re: [PATCH 0/3] arm64: dts: ti: Add Itap Delay Value For High Speed DDR

[Nishanth Menon]

Hi Bhavya Kapoor,

On Fri, 01 Dec 2023 13:50:42 +0530, Bhavya Kapoor wrote:
> This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
> J7200 and for DDR50 speed mode for MMCSD in J721s2 and J784s4 SoC.
> 
> Rebased to next-20231201
> 
> Bhavya Kapoor (3):
>   arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed
>     mode
>   arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed
>     mode
>   arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed
>     mode
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
      commit: 908999561b4340089896b89cef51dae07fc001cb
[2/3] arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
      commit: 4a52a8208568a85b0d51e5ca81be5925973ef108
[3/3] arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode
      commit: 8bbe8a7dbaabb84d93321f116966af73ba6a7233

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D