* [PATCH v4 2/5] clk: imx: imx8mp: Add audiomix block control
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
@ 2023-02-23 17:11 ` Marek Vasut
2023-02-24 16:38 ` Luca Ceresoli
2023-02-23 17:11 ` [PATCH v4 3/5] dt-bindings: clock: " Marek Vasut
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2023-02-23 17:11 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Luca Ceresoli, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Model it as a large static table of
gates and muxes with one exception, which is the PLL14xx . The PLL14xx
SAI PLL has to be registered separately.
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
---
V2: No change
V3: - Use devm_platform_ioremap_resource
- Use clk_hw_onecell_data instead of clk_imx8mp_audiomix_priv
- Include mod_devicetable.h for of_device_id struct
- Use struct clk_parent_data instead of string parent_name
V4: - Fix SAI_MCLK_SEL offset as pointed out by Marco
- Add TB from Luca
- Use devm_clk_hw_register_mux_parent_data_table() and drop
custom devm_clk_hw_register_mux_parent_data() patch, tweak
the indent to be less hideous
- Rebase on next 20230223
---
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mp-audiomix.c | 277 ++++++++++++++++++++++++++
2 files changed, 278 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-imx8mp-audiomix.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index a75d59f7cb8a6..ae9d84ef046ba 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
-obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
+obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
new file mode 100644
index 0000000000000..e4300df88f1ac
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for i.MX8M Plus Audio BLK_CTRL
+ *
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+#include "clk.h"
+
+#define CLKEN0 0x000
+#define CLKEN1 0x004
+#define SAI_MCLK_SEL(n) (0x300 + 4 * (n)) /* n in 0..5 */
+#define PDM_SEL 0x318
+#define SAI_PLL_GNRL_CTL 0x400
+
+#define SAIn_MCLK1_PARENT(n) \
+static const struct clk_parent_data \
+clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = { \
+ { \
+ .fw_name = "sai"__stringify(n), \
+ .name = "sai"__stringify(n) \
+ }, { \
+ .fw_name = "sai"__stringify(n)"_mclk", \
+ .name = "sai"__stringify(n)"_mclk" \
+ }, \
+}
+
+SAIn_MCLK1_PARENT(1);
+SAIn_MCLK1_PARENT(2);
+SAIn_MCLK1_PARENT(3);
+SAIn_MCLK1_PARENT(5);
+SAIn_MCLK1_PARENT(6);
+SAIn_MCLK1_PARENT(7);
+
+static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
+ { .fw_name = "sai1", .name = "sai1" },
+ { .fw_name = "sai2", .name = "sai2" },
+ { .fw_name = "sai3", .name = "sai3" },
+ { .name = "dummy" },
+ { .fw_name = "sai5", .name = "sai5" },
+ { .fw_name = "sai6", .name = "sai6" },
+ { .fw_name = "sai7", .name = "sai7" },
+ { .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+ { .fw_name = "sai2_mclk", .name = "sai2_mclk" },
+ { .fw_name = "sai3_mclk", .name = "sai3_mclk" },
+ { .name = "dummy" },
+ { .fw_name = "sai5_mclk", .name = "sai5_mclk" },
+ { .fw_name = "sai6_mclk", .name = "sai6_mclk" },
+ { .fw_name = "sai7_mclk", .name = "sai7_mclk" },
+ { .fw_name = "spdif_extclk", .name = "spdif_extclk" },
+ { .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
+ { .fw_name = "pdm", .name = "pdm" },
+ { .name = "sai_pll_out_div2" },
+ { .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+ { .name = "dummy" },
+};
+
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
+ { .fw_name = "osc_24m", .name = "osc_24m" },
+ { .name = "dummy" },
+ { .name = "dummy" },
+ { .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
+ { .fw_name = "sai_pll", .name = "sai_pll" },
+ { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
+};
+
+#define CLK_GATE(gname, cname) \
+ { \
+ gname"_cg", \
+ IMX8MP_CLK_AUDIOMIX_##cname, \
+ { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \
+ CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \
+ 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \
+ }
+
+#define CLK_SAIn(n) \
+ { \
+ "sai"__stringify(n)"_mclk1_sel", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {}, \
+ clk_imx8mp_audiomix_sai##n##_mclk1_parents, \
+ ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
+ SAI_MCLK_SEL(n), 1, 0 \
+ }, { \
+ "sai"__stringify(n)"_mclk2_sel", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {}, \
+ clk_imx8mp_audiomix_sai_mclk2_parents, \
+ ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents), \
+ SAI_MCLK_SEL(n), 4, 1 \
+ }, { \
+ "sai"__stringify(n)"_ipg_cg", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG, \
+ { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \
+ CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG \
+ }, { \
+ "sai"__stringify(n)"_mclk1_cg", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1, \
+ { \
+ .fw_name = "sai"__stringify(n)"_mclk1_sel", \
+ .name = "sai"__stringify(n)"_mclk1_sel" \
+ }, NULL, 1, \
+ CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1 \
+ }, { \
+ "sai"__stringify(n)"_mclk2_cg", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2, \
+ { \
+ .fw_name = "sai"__stringify(n)"_mclk2_sel", \
+ .name = "sai"__stringify(n)"_mclk2_sel" \
+ }, NULL, 1, \
+ CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2 \
+ }, { \
+ "sai"__stringify(n)"_mclk3_cg", \
+ IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3, \
+ { \
+ .fw_name = "sai_pll_out_div2", \
+ .name = "sai_pll_out_div2" \
+ }, NULL, 1, \
+ CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3 \
+ }
+
+#define CLK_PDM \
+ { \
+ "pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {}, \
+ clk_imx8mp_audiomix_pdm_parents, \
+ ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents), \
+ PDM_SEL, 2, 0 \
+ }
+
+struct clk_imx8mp_audiomix_sel {
+ const char *name;
+ int clkid;
+ const struct clk_parent_data parent; /* For gate */
+ const struct clk_parent_data *parents; /* For mux */
+ int num_parents;
+ u16 reg;
+ u8 width;
+ u8 shift;
+};
+
+static struct clk_imx8mp_audiomix_sel sels[] = {
+ CLK_GATE("asrc", ASRC_IPG),
+ CLK_GATE("pdm", PDM_IPG),
+ CLK_GATE("earc", EARC_IPG),
+ CLK_GATE("ocrama", OCRAMA_IPG),
+ CLK_GATE("aud2htx", AUD2HTX_IPG),
+ CLK_GATE("earc_phy", EARC_PHY),
+ CLK_GATE("sdma2", SDMA2_ROOT),
+ CLK_GATE("sdma3", SDMA3_ROOT),
+ CLK_GATE("spba2", SPBA2_ROOT),
+ CLK_GATE("dsp", DSP_ROOT),
+ CLK_GATE("dspdbg", DSPDBG_ROOT),
+ CLK_GATE("edma", EDMA_ROOT),
+ CLK_GATE("audpll", AUDPLL_ROOT),
+ CLK_GATE("mu2", MU2_ROOT),
+ CLK_GATE("mu3", MU3_ROOT),
+ CLK_PDM,
+ CLK_SAIn(1),
+ CLK_SAIn(2),
+ CLK_SAIn(3),
+ CLK_SAIn(5),
+ CLK_SAIn(6),
+ CLK_SAIn(7)
+};
+
+static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *priv;
+ struct device *dev = &pdev->dev;
+ void __iomem *base;
+ struct clk_hw *hw;
+ int i;
+
+ priv = devm_kzalloc(dev,
+ struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->num = IMX8MP_CLK_AUDIOMIX_END;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ for (i = 0; i < ARRAY_SIZE(sels); i++) {
+ if (sels[i].num_parents == 1) {
+ hw = devm_clk_hw_register_gate_parent_data(dev,
+ sels[i].name, &sels[i].parent, 0,
+ base + sels[i].reg, sels[i].shift, 0, NULL);
+ } else {
+ hw = devm_clk_hw_register_mux_parent_data_table(dev,
+ sels[i].name, sels[i].parents,
+ sels[i].num_parents, 0,
+ base + sels[i].reg,
+ sels[i].shift, sels[i].width,
+ 0, NULL, NULL);
+ }
+
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->hws[sels[i].clkid] = hw;
+ }
+
+ /* SAI PLL */
+ hw = devm_clk_hw_register_mux_parent_data_table(dev,
+ "sai_pll_ref_sel", clk_imx8mp_audiomix_pll_parents,
+ ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
+ CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL,
+ 0, 2, 0, NULL, NULL);
+ priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
+
+ hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
+ base + 0x400, &imx_1443x_pll);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
+
+ hw = devm_clk_hw_register_mux_parent_data_table(dev,
+ "sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels,
+ ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
+ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+ base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
+
+ hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
+ 0, base + SAI_PLL_GNRL_CTL, 13,
+ 0, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
+
+ hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
+ "sai_pll_out", 0, 1, 2);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+ priv);
+}
+
+static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
+ { .compatible = "fsl,imx8mp-audio-blk-ctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
+
+static struct platform_driver clk_imx8mp_audiomix_driver = {
+ .probe = clk_imx8mp_audiomix_probe,
+ .driver = {
+ .name = "imx8mp-audio-blk-ctrl",
+ .of_match_table = clk_imx8mp_audiomix_of_match,
+ },
+};
+
+module_platform_driver(clk_imx8mp_audiomix_driver);
+
+MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
+MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
+MODULE_LICENSE("GPL");
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 2/5] clk: imx: imx8mp: Add audiomix block control
2023-02-23 17:11 ` [PATCH v4 2/5] clk: imx: imx8mp: Add audiomix block control Marek Vasut
@ 2023-02-24 16:38 ` Luca Ceresoli
0 siblings, 0 replies; 16+ messages in thread
From: Luca Ceresoli @ 2023-02-24 16:38 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Hi Marek,
On Thu, 23 Feb 2023 18:11:11 +0100
Marek Vasut <marex@denx.de> wrote:
> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> series of clock gates and muxes. Model it as a large static table of
> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> SAI PLL has to be registered separately.
>
> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
^ confirmed with v4, works as well
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 3/5] dt-bindings: clock: imx8mp: Add audiomix block control
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
2023-02-23 17:11 ` [PATCH v4 2/5] clk: imx: imx8mp: Add audiomix block control Marek Vasut
@ 2023-02-23 17:11 ` Marek Vasut
2023-02-23 17:11 ` [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX Marek Vasut
` (3 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2023-02-23 17:11 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Rob Herring, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Add DT bindings for this IP.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
---
V2: No change
V3: - Add missed RB from Rob from V1
- Rename audio_ahb to plain ahb
V4: - Rebase on next 20230223
---
.../bindings/clock/imx8mp-audiomix.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
new file mode 100644
index 0000000000000..01b4e1e311cef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP AudioMIX Block Control Binding
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
+ used to control Audio related clock on the SoC.
+
+properties:
+ compatible:
+ const: fsl,imx8mp-audio-blk-ctrl
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ power-domain-names:
+ const: audio
+
+ clocks:
+ minItems: 7
+ maxItems: 7
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: sai1
+ - const: sai2
+ - const: sai3
+ - const: sai5
+ - const: sai6
+ - const: sai7
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
+ for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+
+ clock-controller@30e20000 {
+ #clock-cells = <1>;
+ compatible = "fsl,imx8mp-audio-blk-ctrl";
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_SAI1>,
+ <&clk IMX8MP_CLK_SAI2>,
+ <&clk IMX8MP_CLK_SAI3>,
+ <&clk IMX8MP_CLK_SAI5>,
+ <&clk IMX8MP_CLK_SAI6>,
+ <&clk IMX8MP_CLK_SAI7>;
+ clock-names = "ahb",
+ "sai1", "sai2", "sai3",
+ "sai5", "sai6", "sai7";
+ power-domains = <&pgc_audio>;
+ power-domain-names = "audio";
+ reg = <0x30e20000 0x10000>;
+ };
+
+...
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
2023-02-23 17:11 ` [PATCH v4 2/5] clk: imx: imx8mp: Add audiomix block control Marek Vasut
2023-02-23 17:11 ` [PATCH v4 3/5] dt-bindings: clock: " Marek Vasut
@ 2023-02-23 17:11 ` Marek Vasut
2023-02-27 9:08 ` Alexander Stein
2023-02-23 17:11 ` [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK Marek Vasut
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2023-02-23 17:11 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Luca Ceresoli, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
needed to get audio operational on i.MX8MP .
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
---
V2: - Add AUDIO_AXI clock to audio gpc
- Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock
V3: Rename audio_ahb to plain ahb
V4: - Add RB/TB from Luca
- Rebase on next 20230223
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 153 ++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ca8093ee4d0e4..56d2a6377a5a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -571,6 +571,13 @@ pgc_usb2_phy: power-domain@3 {
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_audio: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_AXI>;
+ };
+
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@@ -1119,6 +1126,152 @@ opp-1000000000 {
};
};
+ aips5: bus@30c00000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ spba-bus@30c00000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ reg = <0x30c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sai1: sai@30c10000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c10000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai2: sai@30c20000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c20000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai@30c30000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c30000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai5: sai@30c50000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c50000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai6: sai@30c60000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c60000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai7: sai@30c80000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c80000 0x10000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ sdma3: dma-controller@30e00000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e00000 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ sdma2: dma-controller@30e10000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ audio_blk_ctrl: blk-ctrl@30e20000 {
+ #clock-cells = <1>;
+ compatible = "fsl,imx8mp-audio-blk-ctrl";
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_SAI1>,
+ <&clk IMX8MP_CLK_SAI2>,
+ <&clk IMX8MP_CLK_SAI3>,
+ <&clk IMX8MP_CLK_SAI5>,
+ <&clk IMX8MP_CLK_SAI6>,
+ <&clk IMX8MP_CLK_SAI7>;
+ clock-names = "ahb",
+ "sai1", "sai2", "sai3",
+ "sai5", "sai6", "sai7";
+ power-domains = <&pgc_audio>;
+ power-domain-names = "audio";
+ reg = <0x30e20000 0x10000>;
+ };
+ };
+
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
2023-02-23 17:11 ` [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX Marek Vasut
@ 2023-02-27 9:08 ` Alexander Stein
2023-02-27 11:38 ` Adam Ford
2023-02-27 13:53 ` Marek Vasut
0 siblings, 2 replies; 16+ messages in thread
From: Alexander Stein @ 2023-02-27 9:08 UTC (permalink / raw)
To: linux-clk, Marek Vasut
Cc: Marek Vasut, Luca Ceresoli, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Hi Marek,
thanks for respinning this series.
Am Donnerstag, 23. Februar 2023, 18:11:13 CET schrieb Marek Vasut:
> Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
> needed to get audio operational on i.MX8MP .
>
> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
> V2: - Add AUDIO_AXI clock to audio gpc
> - Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock
> V3: Rename audio_ahb to plain ahb
> V4: - Add RB/TB from Luca
> - Rebase on next 20230223
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 153 ++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> ca8093ee4d0e4..56d2a6377a5a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -571,6 +571,13 @@ pgc_usb2_phy: power-domain@3 {
> reg =
<IMX8MP_POWER_DOMAIN_USB2_PHY>;
> };
>
> + pgc_audio: power-domain@5 {
> + #power-domain-
cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_AUDIOMIX>;
> + clocks = <&clk
IMX8MP_CLK_AUDIO_ROOT>,
> + <&clk
IMX8MP_CLK_AUDIO_AXI>;
> + };
> +
> pgc_gpu2d: power-domain@6 {
> #power-domain-
cells = <0>;
> reg =
<IMX8MP_POWER_DOMAIN_GPU2D>;
> @@ -1119,6 +1126,152 @@ opp-1000000000 {
> };
> };
>
> + aips5: bus@30c00000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x30c00000 0x400000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + spba-bus@30c00000 {
> + compatible = "fsl,spba-bus", "simple-
bus";
> + reg = <0x30c00000 0x100000>;
Is there an SPBA bus for every AIPS? I'm wondering why some aips do have an
spba below and some do not.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sai1: sai@30c10000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c10000 0x10000>;
> + interrupts = <GIC_SPI 95
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 0 2 0>,
<&sdma2 1 2 0>;
Looking at Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml should the
2nd cell value be 24? This would be true for all other sai nodes.
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + sai2: sai@30c20000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c20000 0x10000>;
> + interrupts = <GIC_SPI 96
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 2 2 0>,
<&sdma2 3 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + sai3: sai@30c30000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c30000 0x10000>;
> + interrupts = <GIC_SPI 50
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 4 2 0>,
<&sdma2 5 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + sai5: sai@30c50000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c50000 0x10000>;
> + interrupts = <GIC_SPI 90
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 8 2 0>,
<&sdma2 9 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + sai6: sai@30c60000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c60000 0x10000>;
> + interrupts = <GIC_SPI 90
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 10 2 0>,
<&sdma2 11 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + sai7: sai@30c80000 {
> + compatible = "fsl,imx8mp-
sai", "fsl,imx8mq-sai";
> + reg = <0x30c80000 0x10000>;
> + interrupts = <GIC_SPI 111
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
> + <&clk
IMX8MP_CLK_DUMMY>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
> + <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
> + clock-names = "bus",
"mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 12 2 0>,
<&sdma2 13 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> + };
> +
> + sdma3: dma-controller@30e00000 {
> + compatible = "fsl,imx8mp-sdma",
"fsl,imx8mq-sdma";
> + reg = <0x30e00000 0x10000>;
> + interrupts = <GIC_SPI 34
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
> + <&clk
IMX8MP_CLK_AUDIO_ROOT>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + fsl,sdma-ram-script-name = "imx/sdma/
sdma-imx7d.bin";
> + };
> +
> + sdma2: dma-controller@30e10000 {
> + compatible = "fsl,imx8mp-sdma",
"fsl,imx8mq-sdma";
> + reg = <0x30e10000 0x10000>;
> + interrupts = <GIC_SPI 103
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&audio_blk_ctrl
IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
> + <&clk
IMX8MP_CLK_AUDIO_ROOT>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + fsl,sdma-ram-script-name = "imx/sdma/
sdma-imx7d.bin";
> + };
> +
> + audio_blk_ctrl: blk-ctrl@30e20000 {
Shouldn't the node name be 'clock-controller@30e20000' as mentioned in the
bindings?
But for the whole series:
Testes-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Best regards,
Alexander
> + #clock-cells = <1>;
> + compatible = "fsl,imx8mp-audio-blk-
ctrl";
> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
> + <&clk IMX8MP_CLK_SAI1>,
> + <&clk IMX8MP_CLK_SAI2>,
> + <&clk IMX8MP_CLK_SAI3>,
> + <&clk IMX8MP_CLK_SAI5>,
> + <&clk IMX8MP_CLK_SAI6>,
> + <&clk IMX8MP_CLK_SAI7>;
> + clock-names = "ahb",
> + "sai1", "sai2",
"sai3",
> + "sai5", "sai6",
"sai7";
> + power-domains = <&pgc_audio>;
> + power-domain-names = "audio";
> + reg = <0x30e20000 0x10000>;
> + };
> + };
> +
> aips4: bus@32c00000 {
> compatible = "fsl,aips-bus", "simple-bus";
> reg = <0x32c00000 0x400000>;
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
2023-02-27 9:08 ` Alexander Stein
@ 2023-02-27 11:38 ` Adam Ford
2023-02-27 12:00 ` Alexander Stein
2023-02-27 13:53 ` Marek Vasut
1 sibling, 1 reply; 16+ messages in thread
From: Adam Ford @ 2023-02-27 11:38 UTC (permalink / raw)
To: Alexander Stein
Cc: linux-clk, Marek Vasut, Luca Ceresoli, Abel Vesa, Fabio Estevam,
Jacky Bai, Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach,
Marco Felsch, Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
On Mon, Feb 27, 2023 at 3:46 AM Alexander Stein
<alexander.stein@ew.tq-group.com> wrote:
>
> Hi Marek,
>
> thanks for respinning this series.
>
> Am Donnerstag, 23. Februar 2023, 18:11:13 CET schrieb Marek Vasut:
> > Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
> > needed to get audio operational on i.MX8MP .
> >
> > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > ---
> > Cc: Abel Vesa <abelvesa@kernel.org>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: Jacky Bai <ping.bai@nxp.com>
> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Marco Felsch <m.felsch@pengutronix.de>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: NXP Linux Team <linux-imx@nxp.com>
> > Cc: Peng Fan <peng.fan@nxp.com>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Cc: Richard Cochran <richardcochran@gmail.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: linux-clk@vger.kernel.org
> > ---
> > V2: - Add AUDIO_AXI clock to audio gpc
> > - Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock
> > V3: Rename audio_ahb to plain ahb
> > V4: - Add RB/TB from Luca
> > - Rebase on next 20230223
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 153 ++++++++++++++++++++++
> > 1 file changed, 153 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> > ca8093ee4d0e4..56d2a6377a5a6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -571,6 +571,13 @@ pgc_usb2_phy: power-domain@3 {
> > reg =
> <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > };
> >
> > + pgc_audio: power-domain@5 {
> > + #power-domain-
> cells = <0>;
> > + reg =
> <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
> > + clocks = <&clk
> IMX8MP_CLK_AUDIO_ROOT>,
> > + <&clk
> IMX8MP_CLK_AUDIO_AXI>;
> > + };
> > +
> > pgc_gpu2d: power-domain@6 {
> > #power-domain-
> cells = <0>;
> > reg =
> <IMX8MP_POWER_DOMAIN_GPU2D>;
> > @@ -1119,6 +1126,152 @@ opp-1000000000 {
> > };
> > };
> >
> > + aips5: bus@30c00000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + reg = <0x30c00000 0x400000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + spba-bus@30c00000 {
> > + compatible = "fsl,spba-bus", "simple-
> bus";
> > + reg = <0x30c00000 0x100000>;
>
> Is there an SPBA bus for every AIPS? I'm wondering why some aips do have an
> spba below and some do not.
The SPBA buses are listed in the TRM, and they appear to be mostly
covering serial devices (UART, SPI, SAI, etc), but some are excluded.
As to why it is this way is more of a question for NXP. Check out
chapter 2 of the TRM for the AIPS memory maps.
adam
>
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + sai1: sai@30c10000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c10000 0x10000>;
> > + interrupts = <GIC_SPI 95
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 0 2 0>,
> <&sdma2 1 2 0>;
>
> Looking at Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml should the
> 2nd cell value be 24? This would be true for all other sai nodes.
>
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + sai2: sai@30c20000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c20000 0x10000>;
> > + interrupts = <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 2 2 0>,
> <&sdma2 3 2 0>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + sai3: sai@30c30000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c30000 0x10000>;
> > + interrupts = <GIC_SPI 50
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 4 2 0>,
> <&sdma2 5 2 0>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + sai5: sai@30c50000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c50000 0x10000>;
> > + interrupts = <GIC_SPI 90
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 8 2 0>,
> <&sdma2 9 2 0>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + sai6: sai@30c60000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c60000 0x10000>;
> > + interrupts = <GIC_SPI 90
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 10 2 0>,
> <&sdma2 11 2 0>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + sai7: sai@30c80000 {
> > + compatible = "fsl,imx8mp-
> sai", "fsl,imx8mq-sai";
> > + reg = <0x30c80000 0x10000>;
> > + interrupts = <GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
> > + <&clk
> IMX8MP_CLK_DUMMY>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
> > + <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
> > + clock-names = "bus",
> "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&sdma2 12 2 0>,
> <&sdma2 13 2 0>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > + };
> > +
> > + sdma3: dma-controller@30e00000 {
> > + compatible = "fsl,imx8mp-sdma",
> "fsl,imx8mq-sdma";
> > + reg = <0x30e00000 0x10000>;
> > + interrupts = <GIC_SPI 34
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
> > + <&clk
> IMX8MP_CLK_AUDIO_ROOT>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name = "imx/sdma/
> sdma-imx7d.bin";
> > + };
> > +
> > + sdma2: dma-controller@30e10000 {
> > + compatible = "fsl,imx8mp-sdma",
> "fsl,imx8mq-sdma";
> > + reg = <0x30e10000 0x10000>;
> > + interrupts = <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
> > + <&clk
> IMX8MP_CLK_AUDIO_ROOT>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name = "imx/sdma/
> sdma-imx7d.bin";
> > + };
> > +
> > + audio_blk_ctrl: blk-ctrl@30e20000 {
>
> Shouldn't the node name be 'clock-controller@30e20000' as mentioned in the
> bindings?
> But for the whole series:
> Testes-by: Alexander Stein <alexander.stein@ew.tq-group.com>
>
> Best regards,
> Alexander
>
> > + #clock-cells = <1>;
> > + compatible = "fsl,imx8mp-audio-blk-
> ctrl";
> > + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
> > + <&clk IMX8MP_CLK_SAI1>,
> > + <&clk IMX8MP_CLK_SAI2>,
> > + <&clk IMX8MP_CLK_SAI3>,
> > + <&clk IMX8MP_CLK_SAI5>,
> > + <&clk IMX8MP_CLK_SAI6>,
> > + <&clk IMX8MP_CLK_SAI7>;
> > + clock-names = "ahb",
> > + "sai1", "sai2",
> "sai3",
> > + "sai5", "sai6",
> "sai7";
> > + power-domains = <&pgc_audio>;
> > + power-domain-names = "audio";
> > + reg = <0x30e20000 0x10000>;
> > + };
> > + };
> > +
> > aips4: bus@32c00000 {
> > compatible = "fsl,aips-bus", "simple-bus";
> > reg = <0x32c00000 0x400000>;
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
2023-02-27 11:38 ` Adam Ford
@ 2023-02-27 12:00 ` Alexander Stein
0 siblings, 0 replies; 16+ messages in thread
From: Alexander Stein @ 2023-02-27 12:00 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, Marek Vasut, Luca Ceresoli, Abel Vesa, Fabio Estevam,
Jacky Bai, Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach,
Marco Felsch, Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Am Montag, 27. Februar 2023, 12:38:10 CET schrieb Adam Ford:
> On Mon, Feb 27, 2023 at 3:46 AM Alexander Stein
>
> <alexander.stein@ew.tq-group.com> wrote:
> > Hi Marek,
> >
> > thanks for respinning this series.
> >
> > Am Donnerstag, 23. Februar 2023, 18:11:13 CET schrieb Marek Vasut:
> > > Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
> > > needed to get audio operational on i.MX8MP .
> > >
> > > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > ---
> > > Cc: Abel Vesa <abelvesa@kernel.org>
> > > Cc: Fabio Estevam <festevam@gmail.com>
> > > Cc: Jacky Bai <ping.bai@nxp.com>
> > > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Cc: Lucas Stach <l.stach@pengutronix.de>
> > > Cc: Marco Felsch <m.felsch@pengutronix.de>
> > > Cc: Michael Turquette <mturquette@baylibre.com>
> > > Cc: NXP Linux Team <linux-imx@nxp.com>
> > > Cc: Peng Fan <peng.fan@nxp.com>
> > > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > > Cc: Richard Cochran <richardcochran@gmail.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Stephen Boyd <sboyd@kernel.org>
> > > Cc: devicetree@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > Cc: linux-clk@vger.kernel.org
> > > ---
> > > V2: - Add AUDIO_AXI clock to audio gpc
> > >
> > > - Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock
> > >
> > > V3: Rename audio_ahb to plain ahb
> > > V4: - Add RB/TB from Luca
> > >
> > > - Rebase on next 20230223
> > >
> > > ---
> > >
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 153 ++++++++++++++++++++++
> > > 1 file changed, 153 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> > > ca8093ee4d0e4..56d2a6377a5a6 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -571,6 +571,13 @@ pgc_usb2_phy: power-domain@3 {
> > >
> > > reg =
> >
> > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> >
> > > };
> > >
> > > + pgc_audio: power-domain@5 {
> > > + #power-domain-
> >
> > cells = <0>;
> >
> > > + reg =
> >
> > <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
> >
> > > + clocks = <&clk
> >
> > IMX8MP_CLK_AUDIO_ROOT>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_AUDIO_AXI>;
> >
> > > + };
> > > +
> > >
> > > pgc_gpu2d: power-domain@6 {
> > >
> > > #power-domain-
> >
> > cells = <0>;
> >
> > > reg =
> >
> > <IMX8MP_POWER_DOMAIN_GPU2D>;
> >
> > > @@ -1119,6 +1126,152 @@ opp-1000000000 {
> > >
> > > };
> > >
> > > };
> > >
> > > + aips5: bus@30c00000 {
> > > + compatible = "fsl,aips-bus", "simple-bus";
> > > + reg = <0x30c00000 0x400000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > +
> > > + spba-bus@30c00000 {
> > > + compatible = "fsl,spba-bus", "simple-
> >
> > bus";
> >
> > > + reg = <0x30c00000 0x100000>;
> >
> > Is there an SPBA bus for every AIPS? I'm wondering why some aips do have
> > an
> > spba below and some do not.
>
> The SPBA buses are listed in the TRM, and they appear to be mostly
> covering serial devices (UART, SPI, SAI, etc), but some are excluded.
> As to why it is this way is more of a question for NXP. Check out
> chapter 2 of the TRM for the AIPS memory maps.
Thanks, I did find those AIPS parts. But the issue regarding SPBA is not so
clear. Apparently the spba compatible is checked by the SDMA driver.
Best regards,
Alexander
> adam
>
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > +
> > > + sai1: sai@30c10000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c10000 0x10000>;
> > > + interrupts = <GIC_SPI 95
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 0 2 0>,
> >
> > <&sdma2 1 2 0>;
> >
> > Looking at Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml should
> > the 2nd cell value be 24? This would be true for all other sai nodes.
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai2: sai@30c20000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c20000 0x10000>;
> > > + interrupts = <GIC_SPI 96
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 2 2 0>,
> >
> > <&sdma2 3 2 0>;
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai3: sai@30c30000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c30000 0x10000>;
> > > + interrupts = <GIC_SPI 50
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 4 2 0>,
> >
> > <&sdma2 5 2 0>;
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai5: sai@30c50000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c50000 0x10000>;
> > > + interrupts = <GIC_SPI 90
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 8 2 0>,
> >
> > <&sdma2 9 2 0>;
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai6: sai@30c60000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c60000 0x10000>;
> > > + interrupts = <GIC_SPI 90
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 10 2 0>,
> >
> > <&sdma2 11 2 0>;
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai7: sai@30c80000 {
> > > + compatible = "fsl,imx8mp-
> >
> > sai", "fsl,imx8mq-sai";
> >
> > > + reg = <0x30c80000 0x10000>;
> > > + interrupts = <GIC_SPI 111
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_DUMMY>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
> >
> > > + <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
> >
> > > + clock-names = "bus",
> >
> > "mclk0", "mclk1", "mclk2", "mclk3";
> >
> > > + dmas = <&sdma2 12 2 0>,
> >
> > <&sdma2 13 2 0>;
> >
> > > + dma-names = "rx", "tx";
> > > + status = "disabled";
> > > + };
> > > + };
> > > +
> > > + sdma3: dma-controller@30e00000 {
> > > + compatible = "fsl,imx8mp-sdma",
> >
> > "fsl,imx8mq-sdma";
> >
> > > + reg = <0x30e00000 0x10000>;
> > > + interrupts = <GIC_SPI 34
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_AUDIO_ROOT>;
> >
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + fsl,sdma-ram-script-name = "imx/sdma/
> >
> > sdma-imx7d.bin";
> >
> > > + };
> > > +
> > > + sdma2: dma-controller@30e10000 {
> > > + compatible = "fsl,imx8mp-sdma",
> >
> > "fsl,imx8mq-sdma";
> >
> > > + reg = <0x30e10000 0x10000>;
> > > + interrupts = <GIC_SPI 103
> >
> > IRQ_TYPE_LEVEL_HIGH>;
> >
> > > + clocks = <&audio_blk_ctrl
> >
> > IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
> >
> > > + <&clk
> >
> > IMX8MP_CLK_AUDIO_ROOT>;
> >
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + fsl,sdma-ram-script-name = "imx/sdma/
> >
> > sdma-imx7d.bin";
> >
> > > + };
> > > +
> > > + audio_blk_ctrl: blk-ctrl@30e20000 {
> >
> > Shouldn't the node name be 'clock-controller@30e20000' as mentioned in the
> > bindings?
> > But for the whole series:
> > Testes-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> >
> > Best regards,
> > Alexander
> >
> > > + #clock-cells = <1>;
> > > + compatible = "fsl,imx8mp-audio-blk-
> >
> > ctrl";
> >
> > > + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
> > > + <&clk IMX8MP_CLK_SAI1>,
> > > + <&clk IMX8MP_CLK_SAI2>,
> > > + <&clk IMX8MP_CLK_SAI3>,
> > > + <&clk IMX8MP_CLK_SAI5>,
> > > + <&clk IMX8MP_CLK_SAI6>,
> > > + <&clk IMX8MP_CLK_SAI7>;
> > > + clock-names = "ahb",
> > > + "sai1", "sai2",
> >
> > "sai3",
> >
> > > + "sai5", "sai6",
> >
> > "sai7";
> >
> > > + power-domains = <&pgc_audio>;
> > > + power-domain-names = "audio";
> > > + reg = <0x30e20000 0x10000>;
> > > + };
> > > + };
> > > +
> > >
> > > aips4: bus@32c00000 {
> > >
> > > compatible = "fsl,aips-bus", "simple-bus";
> > > reg = <0x32c00000 0x400000>;
> >
> > --
> > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > Amtsgericht München, HRB 105018
> > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > http://www.tq-group.com/
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
2023-02-27 9:08 ` Alexander Stein
2023-02-27 11:38 ` Adam Ford
@ 2023-02-27 13:53 ` Marek Vasut
1 sibling, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2023-02-27 13:53 UTC (permalink / raw)
To: Alexander Stein, linux-clk
Cc: Luca Ceresoli, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
On 2/27/23 10:08, Alexander Stein wrote:
[...]
>> + sdma2: dma-controller@30e10000 {
>> + compatible = "fsl,imx8mp-sdma",
> "fsl,imx8mq-sdma";
>> + reg = <0x30e10000 0x10000>;
>> + interrupts = <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&audio_blk_ctrl
> IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
>> + <&clk
> IMX8MP_CLK_AUDIO_ROOT>;
>> + clock-names = "ipg", "ahb";
>> + #dma-cells = <3>;
>> + fsl,sdma-ram-script-name = "imx/sdma/
> sdma-imx7d.bin";
>> + };
>> +
>> + audio_blk_ctrl: blk-ctrl@30e20000 {
>
> Shouldn't the node name be 'clock-controller@30e20000' as mentioned in the
> bindings?
> But for the whole series:
> Testes-by: Alexander Stein <alexander.stein@ew.tq-group.com>
It should be clock-controller indeed, fixed in V5, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
` (2 preceding siblings ...)
2023-02-23 17:11 ` [PATCH v4 4/5] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX Marek Vasut
@ 2023-02-23 17:11 ` Marek Vasut
2023-02-23 17:28 ` Fabio Estevam
2023-02-24 12:59 ` Marco Felsch
2023-02-24 0:24 ` [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Adam Ford
2023-02-27 8:38 ` Alexander Stein
5 siblings, 2 replies; 16+ messages in thread
From: Marek Vasut @ 2023-02-23 17:11 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
This is all that is needed to get analog audio output operational
on i.MX8MP EVK.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
---
V2: No change
V3: No change
V4: - Update codec node name and phandle label
- Use just sound for the sound node name
- Rebase on next 20230223
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 60 ++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 7816853162b3f..9ed94f271ef9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -40,6 +40,16 @@ pcie0_refclk: pcie0-refclk {
clock-frequency = <100000000>;
};
+ reg_audio_pwr: regulator-audio-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "audio-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
@@ -83,6 +93,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ sound {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai3>;
+ audio-codec = <&wm8960>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "Mic Jack", "MICB";
+ };
};
&flexspi {
@@ -344,6 +371,17 @@ &i2c3 {
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
+ clock-names = "mclk";
+ wlf,shared-lrclk;
+ wlf,hp-cfg = <3 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ SPKVDD1-supply = <®_audio_pwr>;
+ };
+
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
@@ -422,6 +460,16 @@ &pwm4 {
status = "okay";
};
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -668,6 +716,18 @@ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK
2023-02-23 17:11 ` [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK Marek Vasut
@ 2023-02-23 17:28 ` Fabio Estevam
2023-02-23 17:39 ` Marek Vasut
2023-02-24 12:59 ` Marco Felsch
1 sibling, 1 reply; 16+ messages in thread
From: Fabio Estevam @ 2023-02-23 17:28 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Abel Vesa, Jacky Bai, Krzysztof Kozlowski,
Laurent Pinchart, Lucas Stach, Marco Felsch, Michael Turquette,
NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Richard Cochran, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, linux-arm-kernel
Hi Marek,
On Thu, Feb 23, 2023 at 2:11 PM Marek Vasut <marex@denx.de> wrote:
> + reg_audio_pwr: regulator-audio-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "audio-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
It seems that "regulator-always-on" could be removed as the regulator
is controlled by the codec.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK
2023-02-23 17:28 ` Fabio Estevam
@ 2023-02-23 17:39 ` Marek Vasut
0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2023-02-23 17:39 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-clk, Abel Vesa, Jacky Bai, Krzysztof Kozlowski,
Laurent Pinchart, Lucas Stach, Marco Felsch, Michael Turquette,
NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Richard Cochran, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, linux-arm-kernel, Luca Ceresoli
On 2/23/23 18:28, Fabio Estevam wrote:
> Hi Marek,
Hi,
> On Thu, Feb 23, 2023 at 2:11 PM Marek Vasut <marex@denx.de> wrote:
>
>> + reg_audio_pwr: regulator-audio-pwr {
>> + compatible = "regulator-fixed";
>> + regulator-name = "audio-pwr";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + regulator-always-on;
>
> It seems that "regulator-always-on" could be removed as the regulator
> is controlled by the codec.
Ah yes
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Thanks
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK
2023-02-23 17:11 ` [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK Marek Vasut
2023-02-23 17:28 ` Fabio Estevam
@ 2023-02-24 12:59 ` Marco Felsch
1 sibling, 0 replies; 16+ messages in thread
From: Marco Felsch @ 2023-02-24 12:59 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Hi Marek,
On 23-02-23, Marek Vasut wrote:
> Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
> This is all that is needed to get analog audio output operational
> on i.MX8MP EVK.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
> V2: No change
> V3: No change
> V4: - Update codec node name and phandle label
> - Use just sound for the sound node name
> - Rebase on next 20230223
> ---
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 60 ++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 7816853162b3f..9ed94f271ef9a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -40,6 +40,16 @@ pcie0_refclk: pcie0-refclk {
> clock-frequency = <100000000>;
> };
>
> + reg_audio_pwr: regulator-audio-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "audio-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> reg_can1_stby: regulator-can1-stby {
> compatible = "regulator-fixed";
> regulator-name = "can1-stby";
> @@ -83,6 +93,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + sound {
> + compatible = "fsl,imx-audio-wm8960";
Can we make use the "simple-audio-card" here? At least the 8mq-evk and
the 8mm-evk is using this as well.
Regards,
Marco
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data()
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
` (3 preceding siblings ...)
2023-02-23 17:11 ` [PATCH v4 5/5] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK Marek Vasut
@ 2023-02-24 0:24 ` Adam Ford
2023-02-27 8:38 ` Alexander Stein
5 siblings, 0 replies; 16+ messages in thread
From: Adam Ford @ 2023-02-24 0:24 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
On Thu, Feb 23, 2023 at 11:12 AM Marek Vasut <marex@denx.de> wrote:
>
> Add an API for clock gate that uses parent_data for the parent instead of
> a string parent_name.
>
For the series:
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
adam
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
> V3: New patch
> V4: - Rebase on next 20230223
> ---
> include/linux/clk-provider.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 842e72a5348fa..92b7c794c6272 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -608,6 +608,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
> __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
> NULL, (flags), (reg), (bit_idx), \
> (clk_gate_flags), (lock))
> +
> +/**
> + * devm_clk_hw_register_gate - register a gate clock with the clock framework
> + * @dev: device that is registering this clock
> + * @name: name of this clock
> + * @parent_data: parent clk data
> + * @flags: framework-specific flags for this clock
> + * @reg: register address to control gating of this clock
> + * @bit_idx: which bit in the register controls gating of this clock
> + * @clk_gate_flags: gate-specific flags for this clock
> + * @lock: shared register lock for this clock
> + */
> +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \
> + reg, bit_idx, clk_gate_flags, \
> + lock) \
> + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
> + (parent_data), (flags), (reg), (bit_idx), \
> + (clk_gate_flags), (lock))
> +
> void clk_unregister_gate(struct clk *clk);
> void clk_hw_unregister_gate(struct clk_hw *hw);
> int clk_gate_is_enabled(struct clk_hw *hw);
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data()
2023-02-23 17:11 [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Marek Vasut
` (4 preceding siblings ...)
2023-02-24 0:24 ` [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data() Adam Ford
@ 2023-02-27 8:38 ` Alexander Stein
2023-02-27 13:47 ` Marek Vasut
5 siblings, 1 reply; 16+ messages in thread
From: Alexander Stein @ 2023-02-27 8:38 UTC (permalink / raw)
To: linux-clk, Marek Vasut
Cc: Marek Vasut, Abel Vesa, Fabio Estevam, Jacky Bai,
Krzysztof Kozlowski, Laurent Pinchart, Lucas Stach, Marco Felsch,
Michael Turquette, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree,
linux-arm-kernel
Hi Marek,
thanks for respinning this series.
Am Donnerstag, 23. Februar 2023, 18:11:10 CET schrieb Marek Vasut:
> Add an API for clock gate that uses parent_data for the parent instead of
> a string parent_name.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
> V3: New patch
> V4: - Rebase on next 20230223
> ---
> include/linux/clk-provider.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 842e72a5348fa..92b7c794c6272 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -608,6 +608,25 @@ struct clk *clk_register_gate(struct device *dev, const
> char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name),
> NULL, \ NULL, (flags), (reg), (bit_idx), \
> (clk_gate_flags), (lock))
> +
> +/**
> + * devm_clk_hw_register_gate - register a gate clock with the clock
> framework + * @dev: device that is registering this clock
> + * @name: name of this clock
> + * @parent_data: parent clk data
> + * @flags: framework-specific flags for this clock
> + * @reg: register address to control gating of this clock
> + * @bit_idx: which bit in the register controls gating of this clock
> + * @clk_gate_flags: gate-specific flags for this clock
> + * @lock: shared register lock for this clock
> + */
> +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data,
> flags, \ + reg,
bit_idx, clk_gate_flags, \
> + lock)
\
> + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
> + (parent_data), (flags), (reg),
(bit_idx), \
> + (clk_gate_flags), (lock))
> +
> void clk_unregister_gate(struct clk *clk);
> void clk_hw_unregister_gate(struct clk_hw *hw);
> int clk_gate_is_enabled(struct clk_hw *hw);
Is it worth to add the parent_data paremeter into existing
devm_clk_hw_register_gate macro? Just adding this new macro for setting
parent_data instead of parent_name seems a bit too much. What if someone wants
to set parent_hw? Add another macro?
Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 1/5] clk: Introduce devm_clk_hw_register_gate_parent_data()
2023-02-27 8:38 ` Alexander Stein
@ 2023-02-27 13:47 ` Marek Vasut
0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2023-02-27 13:47 UTC (permalink / raw)
To: Alexander Stein, linux-clk
Cc: Abel Vesa, Fabio Estevam, Jacky Bai, Krzysztof Kozlowski,
Laurent Pinchart, Lucas Stach, Marco Felsch, Michael Turquette,
NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Richard Cochran, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, linux-arm-kernel
On 2/27/23 09:38, Alexander Stein wrote:
[...]
>> +/**
>> + * devm_clk_hw_register_gate - register a gate clock with the clock
>> framework + * @dev: device that is registering this clock
>> + * @name: name of this clock
>> + * @parent_data: parent clk data
>> + * @flags: framework-specific flags for this clock
>> + * @reg: register address to control gating of this clock
>> + * @bit_idx: which bit in the register controls gating of this clock
>> + * @clk_gate_flags: gate-specific flags for this clock
>> + * @lock: shared register lock for this clock
>> + */
>> +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data,
>> flags, \ + reg,
> bit_idx, clk_gate_flags, \
>> + lock)
> \
>> + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
>> + (parent_data), (flags), (reg),
> (bit_idx), \
>> + (clk_gate_flags), (lock))
>> +
>> void clk_unregister_gate(struct clk *clk);
>> void clk_hw_unregister_gate(struct clk_hw *hw);
>> int clk_gate_is_enabled(struct clk_hw *hw);
>
> Is it worth to add the parent_data paremeter into existing
> devm_clk_hw_register_gate macro? Just adding this new macro for setting
> parent_data instead of parent_name seems a bit too much. What if someone wants
> to set parent_hw? Add another macro?
Yes, another macro seems to be the accepted practice here.
^ permalink raw reply [flat|nested] 16+ messages in thread