From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24EDCEB64DC for ; Sat, 1 Jul 2023 08:22:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229641AbjGAIWb (ORCPT ); Sat, 1 Jul 2023 04:22:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229515AbjGAIWa (ORCPT ); Sat, 1 Jul 2023 04:22:30 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90381BC for ; Sat, 1 Jul 2023 01:22:28 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-9891c73e0fbso475087966b.1 for ; Sat, 01 Jul 2023 01:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688199747; x=1690791747; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=gMzN5ldrDLudsFTYrIWTDNOwJnSoomZPJebktTnoU4I=; b=z0vr7th4jrnuqwOOGzCSY6B5JNYPSI9Q1lAB5/LAiCsFLpgAeHlZ9AP0z3cjr2grLr 10l6wNeJX6XhSKFFjLl9yqKhmuQMZ5///4QLfTrb9Ctwa7DjXs75TxJFGTpwuGR9fggH egDYhRbJuK7VooVdV+BHbDNF8uRt8h+WIp4+2eI9R4NNO9EvdJQLu5FFk7agf80rdsvw 6PFEGk8iC/GhsdXH93Z+EKtepKkCgj26eQevb3URGojIfPgReTD1tcZ0zpa0Gh2TPopR pZDCSaMSd2VhCWVQV4USmsOmFUib+gIvSyi7cZf07sxN37OQdqQwARTdFK+1JBPSBcXL F3Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688199747; x=1690791747; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=gMzN5ldrDLudsFTYrIWTDNOwJnSoomZPJebktTnoU4I=; b=ARYY9uETX3pLejjgmXXBu4tWN0SCPhybf2TFd+Q1B0Mcp0K/6CGszzo/fW0ORWjO7/ XcgMZwIpCN6Xi1U+fak/KhuAp9ZfjWQz5aXZRp87fJjsw57Cg9JjdaV1tv7YMWvhZJPg uvQfholTQbDMYMy5vejioFUvia7KKEM4glYTvm5AtDvAR5j7tDTwGybliM0++8kep3SG HbmMg3MRRiVuooim4ymIgDY3oHMs6KeakGGqi4k7w2IVHYoTyateYIdlJ+otXCYQJ0BO kQfi8v3X77XrbYjssmbUSV7VyOk1xNEOV08E3YZJkhnpoA9d2aLbPCEAFvOQ+QCcxfav ffZg== X-Gm-Message-State: ABy/qLYo/pH2uFa2cZBfWYVLfaPuueNn/bBMq1RaAwZkK7uVmIM+ezcC FmPwEoG285vvQ24MOxVcx8Rs0w== X-Google-Smtp-Source: APBJJlHQQAoTBEsW/Bor8efMuJEWqdkdKXwXOik6r7upNjbyBabBfFtmqbgej0SUq+B2EXp04+tBXg== X-Received: by 2002:a17:907:212a:b0:992:6d73:5696 with SMTP id qo10-20020a170907212a00b009926d735696mr4386219ejb.5.1688199747015; Sat, 01 Jul 2023 01:22:27 -0700 (PDT) Received: from [192.168.10.214] ([217.169.179.6]) by smtp.gmail.com with ESMTPSA id b27-20020a170906195b00b00991e2b5a27dsm6356217eje.37.2023.07.01.01.22.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Jul 2023 01:22:26 -0700 (PDT) Message-ID: Date: Sat, 1 Jul 2023 10:22:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin Cc: conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com, Zong Li , Nick Hu , Greentime Hu , Palmer Dabbelt , Paul Walmsley References: <20230616063210.19063-1-eric.lin@sifive.com> <20230616063210.19063-4-eric.lin@sifive.com> <2437bda9-bbdb-ad80-7201-1e16e1388890@linaro.org> <8c9ed2d4-83ab-ecc0-a300-e6bc8e2047b6@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28/06/2023 18:31, Eric Lin wrote: >>>> >>>>> + - enum: >>>>> + - sifive,pL2Cache0 >>>>> + - sifive,pL2Cache1 >>>> >>>> What is "0" and "1" here? What do these compatibles represent? Why they >>>> do not have any SoC related part? >>> >>> The pL2Cache1 has minor changes in hardware, but it can use the same >>> pl2 cache driver. >> >> Then why aren't they compatible? >> > > The pL2Cache1 has removed some unused bits in the register compared to > pl2Cache0. > From the hardware perspective, they are not compatible but they can > share the same pl2 cache driver in software. So they are compatible... If they were not compatible, you wouldn't be able to use the same match in the driver. > Thus, we would like to keep both. It would be great if you can provide > some suggestions. Thanks. I propose to make them compatible, like every other piece of SoC. I don't see any benefit of having them separate. Best regards, Krzysztof